A Scalable Architecture for Multi Millions Frames per Second CMOS Sensor With Digital Storage

Abstract

This paper describes a 3D Integrated Circuit (3DIC) architecture of a burst image sensor (BIS) with embedded digitization and digital storage. This architecture also proposes a new technique to further increase both the frame rate and the stored image capacity at the cost of a spatial resolution reduction. A 2D monolithic demonstrator that takes into account the constraints of a future 3D-IC imager has been fabricated. Experimental results are presented showing that a frame rate from 5 up to 45 Mega frames per second can be achieved. This fully functional approach paves the way to the very first in-focal- textbfplane digital BIS.