Pub Date : 2018-06-24DOI: 10.1109/NEWCAS.2018.8585559
George S. Maximous, Ali M. Fatahalla, Ashraf Seleym, Tamer A. Ali, H. Mostafa
Triboelectrification effect was known since the ancient Greek time. A triboelectric nanogenerator (TENG) was invented and is used to convert the mechanical energy to the electrical energy. The TENG is a promising candidate for the new transducers generation recommended for energy harvesting. It is used to harvest the mechanical energy with a great number of advantages. In this research, a new diagonal motion mode is proposed and is studied intensively in attached electrode mode using COMSOL finite element analysis. Diagonal motion mode offers a new degree of freedom which is the angle of motion allowing for further energy optimization. A new CAD tool is built based on semi-analytical equations derived from both COMSOL simulation results and theoretical framework. The tool optimizes the energy based on both the angle and the distance of motion in a few seconds which is very time efficient compared to the time consuming COMSOL simulations. The tool results show great consistency with the data obtained from time consuming COMSOL results.
{"title":"A New CAD Tool for Energy Optimization of Diagonal Motion Mode of Attached Electrode Triboelectric Nanogenerators","authors":"George S. Maximous, Ali M. Fatahalla, Ashraf Seleym, Tamer A. Ali, H. Mostafa","doi":"10.1109/NEWCAS.2018.8585559","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585559","url":null,"abstract":"Triboelectrification effect was known since the ancient Greek time. A triboelectric nanogenerator (TENG) was invented and is used to convert the mechanical energy to the electrical energy. The TENG is a promising candidate for the new transducers generation recommended for energy harvesting. It is used to harvest the mechanical energy with a great number of advantages. In this research, a new diagonal motion mode is proposed and is studied intensively in attached electrode mode using COMSOL finite element analysis. Diagonal motion mode offers a new degree of freedom which is the angle of motion allowing for further energy optimization. A new CAD tool is built based on semi-analytical equations derived from both COMSOL simulation results and theoretical framework. The tool optimizes the energy based on both the angle and the distance of motion in a few seconds which is very time efficient compared to the time consuming COMSOL simulations. The tool results show great consistency with the data obtained from time consuming COMSOL results.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124530910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-24DOI: 10.1109/NEWCAS.2018.8585550
Emimal Jabason, M. Ahmad, M. Swamy
Although there is no cure for Alzheimer’s disease (AD), an accurate early diagnosis is essential for health and social care, and will be of great significance when the course of the disease could be reversed through treatment options. Florbetapir positron emission tomography (18F-AV-45 PET) is proven to be the most powerful imaging technique to investigate the deposition of amyloid plaques, one of the potential hallmarks of AD, signifying the onset of AD before it changes the brains structure. In this paper, we propose a novel classification algorithm to discriminate the patients having AD, early mild cognitive impairment (MCI), late MCI, and normal control in 18F-AV-45 PET using shearlet based deep convolutional neural network (CNN). It is known that the conventional CNNs involve convolution and pooling layers, which in fact produce the smoothed representation of data, and this results in losing detailed information. In view of this fact, the conventional CNN is integrated with shearlet transform incorporating the multiresolution details of the data. Once the model is pretrained to transform the input data into a better stacked representation, the resulting final layer is passed to softmax classifier, which returns the probabilities of each class. Through experimental results, it is shown that the performance of the proposed classification framework is superior to that of the traditional CNN in Alzheimer’s disease neuroimaging initiative (ADNI) database in terms of classification accuracy. As a result, it has the potential to distinguish the different stages of AD progression with less clinical prior information.
{"title":"Shearlet based Stacked Convolutional Network for Multiclass Diagnosis of Alzheimer’s Disease using the Florbetapir PET Amyloid Imaging Data","authors":"Emimal Jabason, M. Ahmad, M. Swamy","doi":"10.1109/NEWCAS.2018.8585550","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585550","url":null,"abstract":"Although there is no cure for Alzheimer’s disease (AD), an accurate early diagnosis is essential for health and social care, and will be of great significance when the course of the disease could be reversed through treatment options. Florbetapir positron emission tomography (18F-AV-45 PET) is proven to be the most powerful imaging technique to investigate the deposition of amyloid plaques, one of the potential hallmarks of AD, signifying the onset of AD before it changes the brains structure. In this paper, we propose a novel classification algorithm to discriminate the patients having AD, early mild cognitive impairment (MCI), late MCI, and normal control in 18F-AV-45 PET using shearlet based deep convolutional neural network (CNN). It is known that the conventional CNNs involve convolution and pooling layers, which in fact produce the smoothed representation of data, and this results in losing detailed information. In view of this fact, the conventional CNN is integrated with shearlet transform incorporating the multiresolution details of the data. Once the model is pretrained to transform the input data into a better stacked representation, the resulting final layer is passed to softmax classifier, which returns the probabilities of each class. Through experimental results, it is shown that the performance of the proposed classification framework is superior to that of the traditional CNN in Alzheimer’s disease neuroimaging initiative (ADNI) database in terms of classification accuracy. As a result, it has the potential to distinguish the different stages of AD progression with less clinical prior information.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"122 25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122004900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585517
A. Ardakani, C. Condo, W. Gross
Convolutional Neural Networks (CNNs) are constituted of complex, slow convolutional layers and memory-demanding fully- connected layers. Current pruning techniques can reduce memory accesses and power consumption, but cannot speed up the convolutional layers. In this paper, we introduce a pruning technique able to reduce the number of kernels in convolutional layers of up to 90% with negligible accuracy degradation. We propose an architecture to accelerate fully- connected and convolutional computations within a single computational core, with power$/$energy consumption below mobile devices budget. The proposed pruning technique speeds up convolutional computations by up to $ 6.9times $, reducing memory accesses by the same factor.
{"title":"A Multi-Mode Accelerator for Pruned Deep Neural Networks","authors":"A. Ardakani, C. Condo, W. Gross","doi":"10.1109/NEWCAS.2018.8585517","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585517","url":null,"abstract":"Convolutional Neural Networks (CNNs) are constituted of complex, slow convolutional layers and memory-demanding fully- connected layers. Current pruning techniques can reduce memory accesses and power consumption, but cannot speed up the convolutional layers. In this paper, we introduce a pruning technique able to reduce the number of kernels in convolutional layers of up to 90% with negligible accuracy degradation. We propose an architecture to accelerate fully- connected and convolutional computations within a single computational core, with power$/$energy consumption below mobile devices budget. The proposed pruning technique speeds up convolutional computations by up to $ 6.9times $, reducing memory accesses by the same factor.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123540642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585596
C. Christoffersen, T. Ngo, Ruiqi Song, Yushi Zhou, S. Pichardo, L. Curiel
Recently, integrated class DE amplifiers without matching networks have been proposed as a compact solution to drive piezoelectric ultrasound transducers for high-intensity focused ultrasound (HIFU) therapy. However, when driving a transducer array, it is not always possible to drive all transducers in ideal Class DE conditions due to variations in the impedance of each array element. This paper outlines a method to predict switching losses and to select good driving parameters for an entire array without using matching networks. To the best of the authors knowledge, this is the first paper to present such a method. The method is experimentally validated using an integrated driver developed by the authors.
{"title":"Suboptimal Class DE Operation for Ultrasound Transducer Arrays","authors":"C. Christoffersen, T. Ngo, Ruiqi Song, Yushi Zhou, S. Pichardo, L. Curiel","doi":"10.1109/NEWCAS.2018.8585596","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585596","url":null,"abstract":"Recently, integrated class DE amplifiers without matching networks have been proposed as a compact solution to drive piezoelectric ultrasound transducers for high-intensity focused ultrasound (HIFU) therapy. However, when driving a transducer array, it is not always possible to drive all transducers in ideal Class DE conditions due to variations in the impedance of each array element. This paper outlines a method to predict switching losses and to select good driving parameters for an entire array without using matching networks. To the best of the authors knowledge, this is the first paper to present such a method. The method is experimentally validated using an integrated driver developed by the authors.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115222716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585458
J. Ou, Pietro M. Ferreira
Recent studies have shown that the power consumption of a wake-up receiver can be reduced by using an envelope detector as its first stage. Designing a low power envelope detector is challenging because of stringent requirements such as data rate, operating frequency, conversion gain and sensitivity. This paper describes the design of a 915 MHz envelope detector which uses a combination of active inductors and an input matching circuit to improve its conversion gain. The proposed design consumes 2 $mu mathrm{A}$ of bias current, achieves a 37.8 dB of conversion gain, a sensitivity of -60 dBm and a data rate of 200 kb/s in a 0.13 $mu mathrm{m}$ CMOS process.
{"title":"A CMOS Envelope Detector for Low Power Wireless Receiver Applications","authors":"J. Ou, Pietro M. Ferreira","doi":"10.1109/NEWCAS.2018.8585458","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585458","url":null,"abstract":"Recent studies have shown that the power consumption of a wake-up receiver can be reduced by using an envelope detector as its first stage. Designing a low power envelope detector is challenging because of stringent requirements such as data rate, operating frequency, conversion gain and sensitivity. This paper describes the design of a 915 MHz envelope detector which uses a combination of active inductors and an input matching circuit to improve its conversion gain. The proposed design consumes 2 $mu mathrm{A}$ of bias current, achieves a 37.8 dB of conversion gain, a sensitivity of -60 dBm and a data rate of 200 kb/s in a 0.13 $mu mathrm{m}$ CMOS process.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585629
Sesha Sairam Regulagadda, S. Nagaveni, A. Dutta
An ultra-low-power, 2.4 GHz ZigBee and Bluetooth-low-energy (BLE) direct-conversion-receiver front-end for internet of things (IoT) applications is designed and presented. A common-source (CS) Low-noise-amplifier (LNA) and direct back-gate-coupled quadrature-voltage-controlled-oscillator (QVCO) are reusing the current to reduce the power consumption. A symmetrical AND-type passive mixer which converts 50% local oscillator (LO) signal duty cycle to 25% and trans-impedance-amplifier (TIA), converting single-ended RF into differential base-band without I/Q cross talk. Finally, a programmable low-pass-filter (LPF) makes the receiver to operate in both the standards. The proposed full on chip receiver front end is designed with the UMC 180 nm CMOS technology and post layout simulation result show 42dB of conversion-gain (CG), 14 dB of noise-figure (NF),-15dB of S11 and-16dBm of input referred third order inter modulation intercept point (IIP3). The front end consuming 550 μW of power with 0.8 V supply and occupied an area of 1 mm2.
{"title":"A 550-μW, 2.4-GHz ZigBee/BLE Receiver Front End for IoT applications in 180-nm CMOS","authors":"Sesha Sairam Regulagadda, S. Nagaveni, A. Dutta","doi":"10.1109/NEWCAS.2018.8585629","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585629","url":null,"abstract":"An ultra-low-power, 2.4 GHz ZigBee and Bluetooth-low-energy (BLE) direct-conversion-receiver front-end for internet of things (IoT) applications is designed and presented. A common-source (CS) Low-noise-amplifier (LNA) and direct back-gate-coupled quadrature-voltage-controlled-oscillator (QVCO) are reusing the current to reduce the power consumption. A symmetrical AND-type passive mixer which converts 50% local oscillator (LO) signal duty cycle to 25% and trans-impedance-amplifier (TIA), converting single-ended RF into differential base-band without I/Q cross talk. Finally, a programmable low-pass-filter (LPF) makes the receiver to operate in both the standards. The proposed full on chip receiver front end is designed with the UMC 180 nm CMOS technology and post layout simulation result show 42dB of conversion-gain (CG), 14 dB of noise-figure (NF),-15dB of S11 and-16dBm of input referred third order inter modulation intercept point (IIP3). The front end consuming 550 μW of power with 0.8 V supply and occupied an area of 1 mm2.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130422574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585694
G. Ripamonti, S. Michelis, F. Faccio, S. Saggini, A. Koukab, M. Kayal
The Large Hadron Collider experiments at CERN will use power distribution schemes relying on integrated buck DCIDC converters. Due to the radiation-hardness requirements, the devices used for the development of such converters will have a voltage rating which is close to the converters’ input voltage. The voltage spikes generated during the hard-switching operation can affect the reliability of such low-voltage MOSFETs. A fixed and sufficiently small gate driver current for the high-side switch could be used to guarantee the reliable operation even in the worst-case conditions in terms of input voltage, output current, temperature and process variations. Nevertheless, this would result in a suboptimal efficiency in all the other working conditions. This work presents an integrated system than monitors in real-time the voltage stress, and adjusts the gate driver current to achieve maximum efficiency in all conditions, while ensuring compliance with the reliability specifications. A buck converter including the voltage peak detector and an adjustable gate driver current has been designed in a 130 nm technology, demonstrating the functionality of the voltage stress monitoring system.
{"title":"A Reliability and Efficiency Optimization System for Hard-Switching DC/DC Converters","authors":"G. Ripamonti, S. Michelis, F. Faccio, S. Saggini, A. Koukab, M. Kayal","doi":"10.1109/NEWCAS.2018.8585694","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585694","url":null,"abstract":"The Large Hadron Collider experiments at CERN will use power distribution schemes relying on integrated buck DCIDC converters. Due to the radiation-hardness requirements, the devices used for the development of such converters will have a voltage rating which is close to the converters’ input voltage. The voltage spikes generated during the hard-switching operation can affect the reliability of such low-voltage MOSFETs. A fixed and sufficiently small gate driver current for the high-side switch could be used to guarantee the reliable operation even in the worst-case conditions in terms of input voltage, output current, temperature and process variations. Nevertheless, this would result in a suboptimal efficiency in all the other working conditions. This work presents an integrated system than monitors in real-time the voltage stress, and adjusts the gate driver current to achieve maximum efficiency in all conditions, while ensuring compliance with the reliability specifications. A buck converter including the voltage peak detector and an adjustable gate driver current has been designed in a 130 nm technology, demonstrating the functionality of the voltage stress monitoring system.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131737671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585712
Sanjay Prajapati, Z. Zilic, B. Kaushik
The in-memory computing concept has gained significant attraction with the inception of perpendicular magnetic tunnel junction (PMTJ) device, due to its nonvolatility and CMOS compatibility. Recently, several magnetic full-adder (MFA) designs based on spin-transfer torque (STT) and spin- Hall effect (SHE) magnetic random access memories (MRAMs) have been demonstrated. However, they consume higher write energy and occupy larger area. In this work, a novel MFA using differential spin-Hall (DSH) MRAM is proposed. The DSH- MRAM provides simultaneous switching of two PMTJ devices using SHE and generates complementary logic outputs. The single Hall metal (HM) shared by these PMTJ devices offers a very low resistance path for write operation. In this work, an external magnetic field (EMF) is used to assist the SHE current for PMTJ switching that eliminates the need for a STT current. A SPICE-compatible Verilog-A MTJ behaviour model of the proposed MFA is developed. The EMF-assisted DSH-MRAM requires a very short pulse (300 ps) of SHE current to switch both the PMTJs. The proposed MFA exhibits 65% less time, consumes 93% (18%) less write (read) energy, and saves 23% area compared to recent STT/SHE-MTJ based MFA designs.
{"title":"Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM","authors":"Sanjay Prajapati, Z. Zilic, B. Kaushik","doi":"10.1109/NEWCAS.2018.8585712","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585712","url":null,"abstract":"The in-memory computing concept has gained significant attraction with the inception of perpendicular magnetic tunnel junction (PMTJ) device, due to its nonvolatility and CMOS compatibility. Recently, several magnetic full-adder (MFA) designs based on spin-transfer torque (STT) and spin- Hall effect (SHE) magnetic random access memories (MRAMs) have been demonstrated. However, they consume higher write energy and occupy larger area. In this work, a novel MFA using differential spin-Hall (DSH) MRAM is proposed. The DSH- MRAM provides simultaneous switching of two PMTJ devices using SHE and generates complementary logic outputs. The single Hall metal (HM) shared by these PMTJ devices offers a very low resistance path for write operation. In this work, an external magnetic field (EMF) is used to assist the SHE current for PMTJ switching that eliminates the need for a STT current. A SPICE-compatible Verilog-A MTJ behaviour model of the proposed MFA is developed. The EMF-assisted DSH-MRAM requires a very short pulse (300 ps) of SHE current to switch both the PMTJs. The proposed MFA exhibits 65% less time, consumes 93% (18%) less write (read) energy, and saves 23% area compared to recent STT/SHE-MTJ based MFA designs.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131063571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585511
I. Filanovsky
The paper considers a new design method of transitional filters with characteristics intermediate between that of two polynomial filters with arbitrary denominators of the same order. The method assumes that using two given denominator polynomials one tries to realize two ladder RLC filters (which are called here the “phantom” filters). When the L and C elements of these two ladder “phantom” filters are found, the elements of the transitional “phantom” filter are calculated using linear interpolation between the corresponding Ls and Cs found for given denominator polynomials. Then, using these interpolated values one restores the transitional filter transfer function. The approach is illustrated by design of the transitional filters for the Chebyshev and Butterworth polynomial filters.
{"title":"A New Design Method Of Transitional Polynomial Filters","authors":"I. Filanovsky","doi":"10.1109/NEWCAS.2018.8585511","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585511","url":null,"abstract":"The paper considers a new design method of transitional filters with characteristics intermediate between that of two polynomial filters with arbitrary denominators of the same order. The method assumes that using two given denominator polynomials one tries to realize two ladder RLC filters (which are called here the “phantom” filters). When the L and C elements of these two ladder “phantom” filters are found, the elements of the transitional “phantom” filter are calculated using linear interpolation between the corresponding Ls and Cs found for given denominator polynomials. Then, using these interpolated values one restores the transitional filter transfer function. The approach is illustrated by design of the transitional filters for the Chebyshev and Butterworth polynomial filters.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"11 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132844907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/NEWCAS.2018.8585467
Thibaut Despoisse, A. Ghiotto, P. Busson, N. Deltimple
The combination of Massive MIMO (M-MIMO) and small cells has been selected for the fifth generation (5G) of mobile telecommunication system. But large-scale antenna arrays and extreme densification brings an important power consumption which is not compliant with the energy saving needs. Early studies have excluded fully-digital transmitters due to their high power consumption and complexity. However, the benefits of hybrid beamforming systems may not be so obvious. This paper presents an overview of 5G requirements and prospective solutions. It focuses on the base station transmitter topologies for small cells and compare their power consumption and complexity. As hybrid beamforming is suitable for small arrays covering few users, fully-digital transmitters seems compliant with larger systems to reach 5G targets.
{"title":"A Comparison of Beamforming Schemes for 5G mm-Wave Small Cell Transmitters","authors":"Thibaut Despoisse, A. Ghiotto, P. Busson, N. Deltimple","doi":"10.1109/NEWCAS.2018.8585467","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585467","url":null,"abstract":"The combination of Massive MIMO (M-MIMO) and small cells has been selected for the fifth generation (5G) of mobile telecommunication system. But large-scale antenna arrays and extreme densification brings an important power consumption which is not compliant with the energy saving needs. Early studies have excluded fully-digital transmitters due to their high power consumption and complexity. However, the benefits of hybrid beamforming systems may not be so obvious. This paper presents an overview of 5G requirements and prospective solutions. It focuses on the base station transmitter topologies for small cells and compare their power consumption and complexity. As hybrid beamforming is suitable for small arrays covering few users, fully-digital transmitters seems compliant with larger systems to reach 5G targets.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115391104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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