Scalable Low-Cost Sorting Network with Weighted Bit-Streams

Brady Prince, M. Najafi, Bingzhe Li
{"title":"Scalable Low-Cost Sorting Network with Weighted Bit-Streams","authors":"Brady Prince, M. Najafi, Bingzhe Li","doi":"10.1109/ISQED57927.2023.10129357","DOIUrl":null,"url":null,"abstract":"Sorting is a fundamental function in many applications from data processing to database systems. For high performance, sorting-hardware based sorting designs are implemented by conventional binary or emerging stochastic computing (SC) approaches. Binary designs are fast and energy-efficient but costly to implement. SC-based designs, on the other hand, are area and power-efficient but slow and energy-hungry. So, the previous studies of the hardware-based sorting further faced scalability issues. In this work, we propose a novel scalable low-cost design for implementing sorting networks. We borrow the concept of SC for the area- and power efficiency but use weighted stochastic bit-streams to address the high latency and energy consumption issue of SC designs. A new lock and swap (LAS) unit is proposed to sort weighted bit-streams. The LAS-based sorting network can determine the result of comparing different input values early and then map the inputs to the corresponding outputs based on shorter weighted bit-streams. Experimental results show that the proposed design approach achieves much better hardware scalability than prior work. Especially, as increasing the number of inputs, the proposed scheme can reduce the energy consumption by about 3.8% - 93% compared to prior binary and SC-based designs.","PeriodicalId":315053,"journal":{"name":"2023 24th International Symposium on Quality Electronic Design (ISQED)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 24th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED57927.2023.10129357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

Sorting is a fundamental function in many applications from data processing to database systems. For high performance, sorting-hardware based sorting designs are implemented by conventional binary or emerging stochastic computing (SC) approaches. Binary designs are fast and energy-efficient but costly to implement. SC-based designs, on the other hand, are area and power-efficient but slow and energy-hungry. So, the previous studies of the hardware-based sorting further faced scalability issues. In this work, we propose a novel scalable low-cost design for implementing sorting networks. We borrow the concept of SC for the area- and power efficiency but use weighted stochastic bit-streams to address the high latency and energy consumption issue of SC designs. A new lock and swap (LAS) unit is proposed to sort weighted bit-streams. The LAS-based sorting network can determine the result of comparing different input values early and then map the inputs to the corresponding outputs based on shorter weighted bit-streams. Experimental results show that the proposed design approach achieves much better hardware scalability than prior work. Especially, as increasing the number of inputs, the proposed scheme can reduce the energy consumption by about 3.8% - 93% compared to prior binary and SC-based designs.
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具有加权比特流的可扩展低成本排序网络
从数据处理到数据库系统,排序是许多应用程序中的基本功能。为了获得高性能,基于排序硬件的排序设计是通过传统的二进制或新兴的随机计算(SC)方法实现的。二进制设计快速且节能,但实现起来代价高昂。另一方面,基于sc的设计,面积和功率效率高,但速度慢,耗能大。因此,先前的基于硬件的排序研究进一步面临可伸缩性问题。在这项工作中,我们提出了一种新的可扩展的低成本设计来实现分类网络。我们借用SC的概念来提高面积和功率效率,但使用加权随机比特流来解决SC设计的高延迟和能耗问题。提出了一种新的锁与交换(LAS)单元来对加权比特流进行排序。基于las的排序网络可以提前确定不同输入值比较的结果,然后根据较短的加权比特流将输入映射到相应的输出。实验结果表明,该方法具有较好的硬件可扩展性。特别是,随着输入数量的增加,与先前的二进制和基于sc的设计相比,所提出的方案可以减少约3.8% - 93%的能耗。
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