{"title":"Implant spacer optimization for the improvement of power MOSFETs' unclamped inductive switching (UIS) and high temperature breakdown","authors":"C. Kocon, J. Zeng, R. Stokes","doi":"10.1109/ISPSD.2000.856795","DOIUrl":null,"url":null,"abstract":"This paper proposes an improvement to a 30 V N-Channel Power VDMOSFET's UIS and high temperature breakdown voltage capability by using a non-etched 0.0750 /spl mu/m thin oxide spacer as masking for a high dose body implant in lieu of a power industry accepted 0.3 /spl mu/m-0.5 /spl mu/m etched spacer. This thinner non-etched spacer allows for a more highly concentrated and precise body dopant distribution beneath the source region, for a given implant energy, preventing the parasitic BJT from turning on at high current densities. As a consequence the UIS and high temperature (/spl ges/150/spl deg/C) breakdown characteristics are enhanced without increasing threshold voltage or device on-resistance.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856795","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 15
Abstract
This paper proposes an improvement to a 30 V N-Channel Power VDMOSFET's UIS and high temperature breakdown voltage capability by using a non-etched 0.0750 /spl mu/m thin oxide spacer as masking for a high dose body implant in lieu of a power industry accepted 0.3 /spl mu/m-0.5 /spl mu/m etched spacer. This thinner non-etched spacer allows for a more highly concentrated and precise body dopant distribution beneath the source region, for a given implant energy, preventing the parasitic BJT from turning on at high current densities. As a consequence the UIS and high temperature (/spl ges/150/spl deg/C) breakdown characteristics are enhanced without increasing threshold voltage or device on-resistance.
本文提出了一种改进30 V n沟道功率VDMOSFET的UIS和高温击穿电压能力的方法，通过使用非蚀刻0.0750 /spl μ l /m的薄氧化物间隔片作为高剂量体植入物的掩蔽剂，取代了电力行业接受的0.3 /spl μ l /m-0.5 /spl μ l /m的蚀刻间隔片。对于给定的植入物能量，这种更薄的非蚀刻间隔允许在源区域下更高度集中和精确的体掺杂分布，防止寄生BJT在高电流密度下打开。因此，在不增加阈值电压或器件导通电阻的情况下，UIS和高温(/spl /150/spl℃)击穿特性得到了增强。
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