IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO
{"title":"IBIST/sup TM/ (interconnect built-in self-test) architecture and methodology for pci express: intel's next-generation test and validation methodology for performance IO","authors":"J. Nejedlo","doi":"10.1109/TEST.2003.1270909","DOIUrl":null,"url":null,"abstract":"This paper summarizes the test challenges associated with next -generation platform buses and introduces an Intel-developed technology called IBISTTM (Interconnect Built-In Self-Test) created to meet those challenges. The IBISTTM testing methodology and associated on-die architecture customized for PCI Express (PCIe) interface is described.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Test Conference, 2003. Proceedings. ITC 2003.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2003.1270909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
This paper summarizes the test challenges associated with next -generation platform buses and introduces an Intel-developed technology called IBISTTM (Interconnect Built-In Self-Test) created to meet those challenges. The IBISTTM testing methodology and associated on-die architecture customized for PCI Express (PCIe) interface is described.