Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead—about 4.6% for an 8K 64 SRAM.
{"title":"A built-in self-repair scheme for semiconductor memories with 2-d redundancy","authors":"Jin-Fu Li, J. Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow","doi":"10.1109/TEST.2003.1270863","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270863","url":null,"abstract":"Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns. The BIRA module also serves as the reconfiguration (address remapping) unit in the normal mode. Experimental results show that a high repair rate (i.e., the ratio of the number of repaired memories to the number of defective memories) is achieved with the proposed RA algorithm and BISR scheme. The BISR circuit has a low area overhead—about 4.6% for an 8K 64 SRAM.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-11-06DOI: 10.1109/TEST.2003.1270881
Xiaoyun Sun, L. Kinney, B. Vinnakota
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this paper we first study the reason for strong correlation between Iddq currents for different test vectors, then build a model to estimate the correlation. Based on this model, we propose three test vector selection methods to improve the fault detection ability of ratio-Iddq testing by selecting test vector pairs with the highest correlation. Hspice simulation showed that the fault detection ability can be improved by as much as an order of magnitude. We also describe a test vector partitioning technique to increase the correlation between Iddq currents of different test vectors.
{"title":"Test vector generation based on correlation model for ratio-I/sub DDQ/","authors":"Xiaoyun Sun, L. Kinney, B. Vinnakota","doi":"10.1109/TEST.2003.1270881","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270881","url":null,"abstract":"For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this paper we first study the reason for strong correlation between Iddq currents for different test vectors, then build a model to estimate the correlation. Based on this model, we propose three test vector selection methods to improve the fault detection ability of ratio-Iddq testing by selecting test vector pairs with the highest correlation. Hspice simulation showed that the fault detection ability can be improved by as much as an order of magnitude. We also describe a test vector partitioning technique to increase the correlation between Iddq currents of different test vectors.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134539737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-11-06DOI: 10.1109/TEST.2003.1271075
K. Mohanram, N. Touba
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is based on partial duplication and show that it is capable of reducing the soft error failure rate significantly with a fraction of the overhead required for full duplication. A procedure for characterizing the soft error susceptibility of nodes in a logic circuit, and a heuristic procedure for selecting the set of nodes for partial duplication are described. A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.
{"title":"Cost-effective approach for reducing soft error failure rate in logic circuits","authors":"K. Mohanram, N. Touba","doi":"10.1109/TEST.2003.1271075","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271075","url":null,"abstract":"In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility of nodes in a logic circuit. Rather than target all modeled faults, CED is targeted towards the nodes that have the highest soft error susceptibility to achieve cost-effective tradeoffs between overhead and reduction in the soft error failure rate. Under this new paradigm, we present one particular approach that is based on partial duplication and show that it is capable of reducing the soft error failure rate significantly with a fraction of the overhead required for full duplication. A procedure for characterizing the soft error susceptibility of nodes in a logic circuit, and a heuristic procedure for selecting the set of nodes for partial duplication are described. A full set of experimental results demonstrate the cost-effective tradeoffs that can be achieved.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127833340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-11-06DOI: 10.1109/TEST.2003.1271192
Yong Joon Kim, DongSup Song, YongSeung Shin, S. Chun, Sungho Kang
Complex interconnects in highly integrated system chips are implemented with the bus structures. From a testing point of view, bus-structured systems require more complicated consideration than simple wiring networks since a bus line receives data from many drivers. Therefore, some faults are detected all the time and others are detected only at a particular time. We propose a new interconnect test algorithm for bus structures. The MD+ algorithm supports maximal diagnosis for the bus-structured system and its test period is shorter than the previous algorithms. Moreover, the MD+ algorithm is easy to apply since it is based on a complete diagnosis algorithm for wiring networks. The effectiveness of the MD+ algorithm is confirmed by comparing the test length with previous bus-based interconnect test algorithms.
{"title":"A new maximal diagnosis algorithm for bus-structured systems","authors":"Yong Joon Kim, DongSup Song, YongSeung Shin, S. Chun, Sungho Kang","doi":"10.1109/TEST.2003.1271192","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271192","url":null,"abstract":"Complex interconnects in highly integrated system chips are implemented with the bus structures. From a testing point of view, bus-structured systems require more complicated consideration than simple wiring networks since a bus line receives data from many drivers. Therefore, some faults are detected all the time and others are detected only at a particular time. We propose a new interconnect test algorithm for bus structures. The MD+ algorithm supports maximal diagnosis for the bus-structured system and its test period is shorter than the previous algorithms. Moreover, the MD+ algorithm is easy to apply since it is based on a complete diagnosis algorithm for wiring networks. The effectiveness of the MD+ algorithm is confirmed by comparing the test length with previous bus-based interconnect test algorithms.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132745886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-11-06DOI: 10.1109/TEST.2003.1270822
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, F. Huang, Hong-Tzer Yang
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.
{"title":"Fault pattern oriented defect diagnosis for memories","authors":"Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, F. Huang, Hong-Tzer Yang","doi":"10.1109/TEST.2003.1270822","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270822","url":null,"abstract":"Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experiences of the FA engineer is time consuming and error prone. The increasing time-to-volume pressure on semiconductor products calls for new development flow that enables the product to reach a profitable yield level as soon as possible. Demand in methodologies that allow FA automation thus increases rapidly in recent years. This paper proposes a systematic diagnosis approach based on failure patterns and functional fault models of semiconductor memories. By circuit-level simulation and analysis, we have also developed a fault pattern generator. Defect diagnosis and FA can be performed automatically by using the fault patterns, reducing the time in yield improvement. The main contribution of the paper is thus a methodology and procedure for accelerating FA and yield optimization for semiconductor memories.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123007884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-10-01DOI: 10.1109/TEST.2003.1271107
Arun A. Joseph, H. Kerkhoff
Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconductor electronics (SCE) is capable of handling some of these high-end tasks. We have started a defect-oriented test methodology for SCE, so that reliable systems can be implemented in this technology. In this paper, the details of the study on the Rapid Single-Flux Quantum (RSFQ) process are presented. We present common defects in the SCE processes and corresponding test methodologies to detect them. The (measurement) results prove that we are able to detect possible random defects for statistical purposes in yield analysis. This paper also presents possible test methodologies for RSFQ circuits based on defect oriented testing (DOT).
{"title":"Towards structural testing of superconductor electronics","authors":"Arun A. Joseph, H. Kerkhoff","doi":"10.1109/TEST.2003.1271107","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271107","url":null,"abstract":"Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconductor electronics (SCE) is capable of handling some of these high-end tasks. We have started a defect-oriented test methodology for SCE, so that reliable systems can be implemented in this technology. In this paper, the details of the study on the Rapid Single-Flux Quantum (RSFQ) process are presented. We present common defects in the SCE processes and corresponding test methodologies to detect them. The (measurement) results prove that we are able to detect possible random defects for statistical purposes in yield analysis. This paper also presents possible test methodologies for RSFQ circuits based on defect oriented testing (DOT).","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129197671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271129
J. Paviol
Intersil Corporation – Wireless Division has used University R&D in the past to generate ideas for WAT PCM level self-testing with some success, but has not yet capitalized on all the opportunities possible through university collaborations. Generally the design R&D area has generated the largest payback with new theory, measurement techniques or calibrations, and circuit topology or ideas as the main areas of University – Industry teamwork.
{"title":"ITC2003 improving wireless product testing: an opportunity for university and industry collaboration","authors":"J. Paviol","doi":"10.1109/TEST.2003.1271129","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271129","url":null,"abstract":"Intersil Corporation – Wireless Division has used University R&D in the past to generate ideas for WAT PCM level self-testing with some success, but has not yet capitalized on all the opportunities possible through university collaborations. Generally the design R&D area has generated the largest payback with new theory, measurement techniques or calibrations, and circuit topology or ideas as the main areas of University – Industry teamwork.","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116805017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271157
J. Khare
The fabless model has proven immensely successful for IC companies over the last decade. However, at smaller geometries, process-design interactions are causing design marginality and reliability failures. This paper argues that systematic application of DFM techniques is needed in fabless companies to reduce such (potentially catastrophic} failures. As IC manufacturing technology shifts to 0.13um and below, process-design interactions are becoming very complex. On-chip process variations, pattem-dependent failures, increased via failure rate, etc. are making it harder to separate the process from design using "simplified" design rules. In addition, process ramps have become longer, forcing designs into not-so-stable processes. Such a paradigm is new for engineers in fabless companies, who have traditionally been isolated from the process through the interface of design rules and process comers. As a result, an increasing number of SoCs are being designed by fabless companies without understanding the process-design interaction, resulting in
{"title":"Dfm - a fabless perspective","authors":"J. Khare","doi":"10.1109/TEST.2003.1271157","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271157","url":null,"abstract":"The fabless model has proven immensely successful for IC companies over the last decade. However, at smaller geometries, process-design interactions are causing design marginality and reliability failures. This paper argues that systematic application of DFM techniques is needed in fabless companies to reduce such (potentially catastrophic} failures. As IC manufacturing technology shifts to 0.13um and below, process-design interactions are becoming very complex. On-chip process variations, pattem-dependent failures, increased via failure rate, etc. are making it harder to separate the process from design using \"simplified\" design rules. In addition, process ramps have become longer, forcing designs into not-so-stable processes. Such a paradigm is new for engineers in fabless companies, who have traditionally been isolated from the process through the interface of design rules and process comers. As a result, an increasing number of SoCs are being designed by fabless companies without understanding the process-design interaction, resulting in","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127526406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1271130
I. Harris
The noise-, process-, thermaland power-induced delay variations make circuit delays much less predictable. At the same time, due to small and subtle defects, devices are more likely to marginally violate performance specifications under scaled technologies. Like the signal lines, clock lines are also becoming more susceptible to variations and defects. For timing verification, such trends invalidate traditional, static (i.e. vector-less) timing verification paradigms and create a demand for dynamic solutions that would require carefully crafted test vectors for accurate timing simulation. For delay testing, we need test vectors that can exercise various worst-case timing scenarios to screen out devices with parametric variations and small timing defects. To reduce the overall costs and effort involved in design and test, we need to develop models, tools, and methodologies that can generate high quality, cost-effective test vectors that serve both applications [1].
{"title":"The confluence of manufacturing test and design validation","authors":"I. Harris","doi":"10.1109/TEST.2003.1271130","DOIUrl":"https://doi.org/10.1109/TEST.2003.1271130","url":null,"abstract":"The noise-, process-, thermaland power-induced delay variations make circuit delays much less predictable. At the same time, due to small and subtle defects, devices are more likely to marginally violate performance specifications under scaled technologies. Like the signal lines, clock lines are also becoming more susceptible to variations and defects. For timing verification, such trends invalidate traditional, static (i.e. vector-less) timing verification paradigms and create a demand for dynamic solutions that would require carefully crafted test vectors for accurate timing simulation. For delay testing, we need test vectors that can exercise various worst-case timing scenarios to screen out devices with parametric variations and small timing defects. To reduce the overall costs and effort involved in design and test, we need to develop models, tools, and methodologies that can generate high quality, cost-effective test vectors that serve both applications [1].","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126049712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-09-30DOI: 10.1109/TEST.2003.1270846
K. Wilsher
An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus providing precise logic transition time information from deep inside the chip, greatly aiding failure analysis. The method could also make time measurement of switching events inside an IC when it is mounted in a printed circuit board environment, enabling correlation of these events to board level logic timing, i.e. system validation..
{"title":"Designed -in-diagnostics: a new optical method","authors":"K. Wilsher","doi":"10.1109/TEST.2003.1270846","DOIUrl":"https://doi.org/10.1109/TEST.2003.1270846","url":null,"abstract":"An in-circuit diagnostic test structure triggered by a light pulse captures logic states on-chip with picosecond timing accuracy, and the results read out via a scan chain thus providing precise logic transition time information from deep inside the chip, greatly aiding failure analysis. The method could also make time measurement of switching events inside an IC when it is mounted in a printed circuit board environment, enabling correlation of these events to board level logic timing, i.e. system validation..","PeriodicalId":236182,"journal":{"name":"International Test Conference, 2003. Proceedings. ITC 2003.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123750790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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