{"title":"Advanced circuit technology to realize post giga-bit DRAM","authors":"T. Okuda","doi":"10.1109/ISMVL.1998.679266","DOIUrl":null,"url":null,"abstract":"A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each level corresponding to the two-bit-data storage of a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier that uses charge coupling and charge sharing was developed for the four level sensing and restoring operations. A 4-Gb DRAM was fabricated using 0.15-/spl mu/m CMOS technology, that measures 986 mm/sup 2/ in area. The area of the memory cell is 0.23 /spl mu/m/sup 2/. Its capacitance of 60 fF is achieved by use of a high-dielectric-constant material (Ba,Sr)TiO/sub 3/.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1998.679266","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each level corresponding to the two-bit-data storage of a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier that uses charge coupling and charge sharing was developed for the four level sensing and restoring operations. A 4-Gb DRAM was fabricated using 0.15-/spl mu/m CMOS technology, that measures 986 mm/sup 2/ in area. The area of the memory cell is 0.23 /spl mu/m/sup 2/. Its capacitance of 60 fF is achieved by use of a high-dielectric-constant material (Ba,Sr)TiO/sub 3/.
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