Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679269
T. Itoh, T. Waho, K. Maezawa, Masafumi Yamamoto
We investigate the performance of ultrafast ternary quantizers using resonant tunneling diodes (RTDs) and high-electron mobility transistors (HEMTs) through circuit simulation and experiments. We first analyze the operation of a quantizer by circuit simulation and studied the factors limiting its performance. We then fabricated a ternary quantizer using InP-based RTDs and 0.7-/spl mu/m HEMTs. A three-valued return-to-zero type waveform was observed at a clock frequency of 10 GHz and an input frequency of 3 GHz.
{"title":"Ultrafast ternary quantizer using resonant tunneling devices","authors":"T. Itoh, T. Waho, K. Maezawa, Masafumi Yamamoto","doi":"10.1109/ISMVL.1998.679269","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679269","url":null,"abstract":"We investigate the performance of ultrafast ternary quantizers using resonant tunneling diodes (RTDs) and high-electron mobility transistors (HEMTs) through circuit simulation and experiments. We first analyze the operation of a quantizer by circuit simulation and studied the factors limiting its performance. We then fabricated a ternary quantizer using InP-based RTDs and 0.7-/spl mu/m HEMTs. A three-valued return-to-zero type waveform was observed at a clock frequency of 10 GHz and an input frequency of 3 GHz.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122488065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679345
Lawrence J. Thaden
This MVL is constructed after the pattern of Boolean logic by examining the properties of Boolean logic and extending them to meet the requirements for a three-valued instead of a two-valued logic. Once constructed, the relationships for a subset of this MVL, are illustrated using raster graphics.
{"title":"Constructing an MVL patterned after Boolean logic using a practical approach","authors":"Lawrence J. Thaden","doi":"10.1109/ISMVL.1998.679345","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679345","url":null,"abstract":"This MVL is constructed after the pattern of Boolean logic by examining the properties of Boolean logic and extending them to meet the requirements for a three-valued instead of a two-valued logic. Once constructed, the relationships for a subset of this MVL, are illustrated using raster graphics.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"29 21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122621312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679450
M. Abd-El-Barr, M. Abd-El-Barr
A new algorithm, called the Frontiers algorithm, for optimizing the number of product terms required for the implementation of monotonic and permuted monotonic MVL functions is proposed. All experimental system restricted to the case of 2 variable 4-valued set of logic functions has been programmed using the C language and was interfaced to the HAMLET CAD tool to implement the proposed algorithm. The system was tested using 2231 randomly generated monotonic and permuted monotonic functions. The results obtained indicate that the frontiers-based algorithm compares favorably to existing heuristic minimization techniques with the added advantage that it requires less number of implicants to represent the target functions.
{"title":"A Frontier algorithm for optimization of multiple-valued logic functions","authors":"M. Abd-El-Barr, M. Abd-El-Barr","doi":"10.1109/ISMVL.1998.679450","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679450","url":null,"abstract":"A new algorithm, called the Frontiers algorithm, for optimizing the number of product terms required for the implementation of monotonic and permuted monotonic MVL functions is proposed. All experimental system restricted to the case of 2 variable 4-valued set of logic functions has been programmed using the C language and was interfaced to the HAMLET CAD tool to implement the proposed algorithm. The system was tested using 2231 randomly generated monotonic and permuted monotonic functions. The results obtained indicate that the frontiers-based algorithm compares favorably to existing heuristic minimization techniques with the added advantage that it requires less number of implicants to represent the target functions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131791819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679467
V. Cheushev, V. Shmerko, D. Simovici, S. Yanushkevich
We introduce a technique to compute several information estimations for Boolean and multivalued functions. Special features of these estimations for completely and incompletely specified logic functions, including symmetric logic functions are investigated. Finally, we give an algorithm for determining various information measures for logical functions based on decision trees.
{"title":"Functional entropy and decision trees","authors":"V. Cheushev, V. Shmerko, D. Simovici, S. Yanushkevich","doi":"10.1109/ISMVL.1998.679467","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679467","url":null,"abstract":"We introduce a technique to compute several information estimations for Boolean and multivalued functions. Special features of these estimations for completely and incompletely specified logic functions, including symmetric logic functions are investigated. Finally, we give an algorithm for determining various information measures for logical functions based on decision trees.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132971552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679320
Jing Shen, K. Tanno, O. Ishizuka, Zheng Tang
A highly-functional device called Neuron-MOS Transistor (vMOS) has been applied to implementing new-architecture basic current-mode multi-valued logic (MVL) circuits. The novel current mirror and threshold detector circuits using vMOS are described in this paper. As compared to conventional CMOS circuits the vMOS current mirror has advantages of low-power and high-swing while the vMOS threshold detector has better discrimination ability. Furthermore, the MVL functional circuit-current-mode quaternary T-gate basing vMOS is presented. Performances of the circuits are confirmed by HSPICE simulations.
神经元- mos晶体管(neural - mos Transistor, vMOS)是一种高性能器件，可用于实现新结构的基本电流模多值逻辑电路(MVL)。本文介绍了一种新型的vMOS电流反射镜和阈值检测器电路。与传统CMOS电路相比，vMOS电流反射镜具有低功耗、高摆幅的优点，而vMOS阈值检测器具有更好的判别能力。在此基础上，提出了基于vMOS的电流型四元t栅MVL功能电路。通过HSPICE仿真验证了电路的性能。
{"title":"Application of neuron-MOS to current-mode multi-valued logic circuits","authors":"Jing Shen, K. Tanno, O. Ishizuka, Zheng Tang","doi":"10.1109/ISMVL.1998.679320","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679320","url":null,"abstract":"A highly-functional device called Neuron-MOS Transistor (vMOS) has been applied to implementing new-architecture basic current-mode multi-valued logic (MVL) circuits. The novel current mirror and threshold detector circuits using vMOS are described in this paper. As compared to conventional CMOS circuits the vMOS current mirror has advantages of low-power and high-swing while the vMOS threshold detector has better discrimination ability. Furthermore, the MVL functional circuit-current-mode quaternary T-gate basing vMOS is presented. Performances of the circuits are confirmed by HSPICE simulations.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114861913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679473
H. Tatsumi, Tomoyuki Araki, M. Mukaidono, S. Tokumasu
This paper describes an estimation on the size of n-variable fuzzy switching functions with arbitrary constants ("fuzzy/c" for short). The whole set of fuzzy/c switching functions is divided into equivalence classes called c/sub r/-equivalent. Estimating the number of these functions in each equivalence class can be reduced to enumerating disjunctive forms of a binary switching function, which can be solved by enumerating anti-chains of the partially ordered set composed of simple phrases. Using an improved method for estimating the number of anti-chains, we can get upper and lower bounds on the number of n-variable fuzzy/c switching functions.
{"title":"Upper and lower bounds on the number of fuzzy/c switching functions","authors":"H. Tatsumi, Tomoyuki Araki, M. Mukaidono, S. Tokumasu","doi":"10.1109/ISMVL.1998.679473","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679473","url":null,"abstract":"This paper describes an estimation on the size of n-variable fuzzy switching functions with arbitrary constants (\"fuzzy/c\" for short). The whole set of fuzzy/c switching functions is divided into equivalence classes called c/sub r/-equivalent. Estimating the number of these functions in each equivalence class can be reduced to enumerating disjunctive forms of a binary switching function, which can be solved by enumerating anti-chains of the partially ordered set composed of simple phrases. Using an improved method for estimating the number of anti-chains, we can get upper and lower bounds on the number of n-variable fuzzy/c switching functions.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115111738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679331
C. Files, M. Perkowski
In the past few years, several authors have presented methods of using functional decomposition as applied to machine learning. These authors explore the ideas of functional decomposition, but left the concepts of machine learning to the papers that they reference. In general, they never fully explain why a logic synthesis method should be applied to machine learning. This paper explores and presents the basic concepts of machine learning, and how some concepts match nicely with multi-valued logic synthesis, while others pose great difficulties. The main reason for using multi-valued synthesis is that many problems are naturally multi-valued (i.e., values taken from a discrete set). Thus, mapping the problem directly to a multi-valued set of inputs and outputs is much more natural than encoding the problem into a binary form. The paper also shows that any multi-valued logic synthesis method could be applied to the machine learning problem. But, this paper focuses on multivalued functional decomposition because of its generality of minimizing a given data set.
{"title":"Multi-valued functional decomposition as a machine learning method","authors":"C. Files, M. Perkowski","doi":"10.1109/ISMVL.1998.679331","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679331","url":null,"abstract":"In the past few years, several authors have presented methods of using functional decomposition as applied to machine learning. These authors explore the ideas of functional decomposition, but left the concepts of machine learning to the papers that they reference. In general, they never fully explain why a logic synthesis method should be applied to machine learning. This paper explores and presents the basic concepts of machine learning, and how some concepts match nicely with multi-valued logic synthesis, while others pose great difficulties. The main reason for using multi-valued synthesis is that many problems are naturally multi-valued (i.e., values taken from a discrete set). Thus, mapping the problem directly to a multi-valued set of inputs and outputs is much more natural than encoding the problem into a binary form. The paper also shows that any multi-valued logic synthesis method could be applied to the machine learning problem. But, this paper focuses on multivalued functional decomposition because of its generality of minimizing a given data set.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126002041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679434
A. Ngom, I. Stojmenovic, Z. Obradovic
We address the problem of computing and learning multivalued multithreshold perceptrons. Every n-input X-valued logic function can be implemented using a (k, s)-perceptron, for some number of thresholds s. We propose a genetic algorithm to search for an optimal (k, s)-perceptron that efficiently realizes a given multiple-valued logic function, that is to minimize the number of thresholds. Experimental results show that the genetic algorithm find optimal solutions in most cases.
{"title":"Minimization of multivalued multithreshold perceptrons using genetic algorithms","authors":"A. Ngom, I. Stojmenovic, Z. Obradovic","doi":"10.1109/ISMVL.1998.679434","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679434","url":null,"abstract":"We address the problem of computing and learning multivalued multithreshold perceptrons. Every n-input X-valued logic function can be implemented using a (k, s)-perceptron, for some number of thresholds s. We propose a genetic algorithm to search for an optimal (k, s)-perceptron that efficiently realizes a given multiple-valued logic function, that is to minimize the number of thresholds. Experimental results show that the genetic algorithm find optimal solutions in most cases.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127264465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679471
Katsuhiko Shimabukuro, Chotei Zukeran
This paper presents new reconfigurable multiple-valued residue arithmetic circuits, in which multiplication and addition can be performed alternatively. In order to construct the reconfigurable arithmetic circuits, we develop shifting-based hardware algorithms for both mod m/sub i/ multipliers and mod m/sub i/ adders. The proposed algorithms utilize three-valued one-hot coding for the representation of each residue digit effectively. By the coding, mod m/sub i/ multiplication can be simply performed by a shift operation and sign inversion. In mod m addition, the operation is decomposed into several operations, which include an inverse operation, two multiplications and an increment operation. It is demonstrated that the proposed hardware algorithms of residue arithmetic are useful to implement the reconfigurable current-mode multiple-valued residue arithmetic circuits, which are comparable to the conventional ones.
{"title":"Reconfigurable current-mode multiple-valued residue arithmetic circuits","authors":"Katsuhiko Shimabukuro, Chotei Zukeran","doi":"10.1109/ISMVL.1998.679471","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679471","url":null,"abstract":"This paper presents new reconfigurable multiple-valued residue arithmetic circuits, in which multiplication and addition can be performed alternatively. In order to construct the reconfigurable arithmetic circuits, we develop shifting-based hardware algorithms for both mod m/sub i/ multipliers and mod m/sub i/ adders. The proposed algorithms utilize three-valued one-hot coding for the representation of each residue digit effectively. By the coding, mod m/sub i/ multiplication can be simply performed by a shift operation and sign inversion. In mod m addition, the operation is decomposed into several operations, which include an inverse operation, two multiplications and an increment operation. It is demonstrated that the proposed hardware algorithms of residue arithmetic are useful to implement the reconfigurable current-mode multiple-valued residue arithmetic circuits, which are comparable to the conventional ones.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116676252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-05-27DOI: 10.1109/ISMVL.1998.679273
Y. Nagata, D. M. Miller, M. Mukaidono
For fault diagnosis in R-valued PLAs (R/spl ges/2), we construct a test table with rows of test vectors each giving activated product lines and normal output values of the programmed functions. Test vector generation for constructing the test table is based on product-oriented test generation which was proposed by Min and Fujiwara for binary PLAs. The number of test vectors is exactly k/spl middot/(n/spl middot/R-1) where k is the number of product lines in an R-valued n variable PLA. The procedure to construct the test table is based on a hash method on the generated tests. By combining tests in the table, fault diagnosis of PLA can be performed efficiently.
{"title":"Minimal test set generation for fault diagnosis in R-valued PLAs","authors":"Y. Nagata, D. M. Miller, M. Mukaidono","doi":"10.1109/ISMVL.1998.679273","DOIUrl":"https://doi.org/10.1109/ISMVL.1998.679273","url":null,"abstract":"For fault diagnosis in R-valued PLAs (R/spl ges/2), we construct a test table with rows of test vectors each giving activated product lines and normal output values of the programmed functions. Test vector generation for constructing the test table is based on product-oriented test generation which was proposed by Min and Fujiwara for binary PLAs. The number of test vectors is exactly k/spl middot/(n/spl middot/R-1) where k is the number of product lines in an R-valued n variable PLA. The procedure to construct the test table is based on a hash method on the generated tests. By combining tests in the table, fault diagnosis of PLA can be performed efficiently.","PeriodicalId":377860,"journal":{"name":"Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114139672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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