Design and simulation of hybrid SET-MOS pass transistor logic based universal logic gates

A. Jain, A. Ghosh, S. Sarkar
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引用次数: 2

Abstract

In order to improve density of integration in VLSI chips and to ensure ultra low power dissipation Co-design of MOS transistor along with Single electron transistor is considered as one of the best option to work with. In the present work we have designed universal logic gates using hybrid SET-MOS based pass transistor logic. The logic gates are consists of one Single electron transistor and one NMOS transistor, both are working as pass transistors. In this paper we have designed NAND and NOR logic gates by providing inputs in their original and complemented form to the different nodes of the pass transistors depending upon the realization of that particular logic gate.
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基于通用逻辑门的混合SET-MOS通管逻辑的设计与仿真
为了提高VLSI芯片的集成密度和保证超低功耗,MOS晶体管与单电子晶体管的协同设计被认为是最佳的选择之一。在本工作中,我们采用基于混合SET-MOS的通管逻辑设计了通用逻辑门。逻辑门由一个单电子晶体管和一个NMOS晶体管组成,两者都作为通路晶体管工作。在本文中,我们通过根据特定逻辑门的实现向通路晶体管的不同节点提供原始和补充形式的输入来设计NAND和NOR逻辑门。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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