Automatic parallelization of a Petri net-based design representation for high-level synthesis

Abstract

This paper presents an approach to automatic parallelization of an internal design representation for high-level synthesis of hardware structures. It concentrates on aspects which are specific to the parallelization of the Petri net based representation used by our design environment. Preservation of safeness and conflict freeness of the internal representation during parallelization are basic requirements for the correctness of the resulted hardware. A hierarchical Petri net structure has been used as an intermediate representation during parallelization, which results in an important reduction of the complexity of the parallelization process. Experimental results demonstrate the efficiency our approach in the context of the CAMAD high-level synthesis system.