Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

Abstract

This paper presents an efficient procedure to improve logic testing for bridging faults (BF) in CMOS circuits. A unified procedure is presented that extracts the test vector from transistor level networks, which will reduce the occurrence of intermediate voltage that leads to Byzantine General's problems and feedback oscillation. By using this procedure according to fault location, the fault coverage of logic testing will increase without using both simulation and a complex calculation for predicting bridging voltage or logic threshold of the driven gates.