High Speed Hardware for March C¯

M. Saha, Souvik Das, B. Sikdar
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引用次数: 6

Abstract

The variations of March tests are extensively used for functional test of SRAMs and DRAMs. This work proposes hardware realization of March C- to enable efficient fault detection in memories. The properties of single length cycle attractor cellular automata are exploited to memorize the status (faulty/non-faulty) of memory words during read (r0/r1) operation of the March C- algorithm. It effectively reduces the overhead of comparison that is required in a conventional test structure, to take decision on the faults in memory.
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高速硬件三月C¯
March测试的变体被广泛用于sram和dram的功能测试。本文提出了March C-的硬件实现,以实现存储器中有效的故障检测。利用单长周期吸引子元胞自动机的特性,对March C-算法的读(0/r1)操作中记忆字的状态(故障/非故障)进行记忆。它有效地减少了在传统测试结构中对内存中的错误做出决策所需的比较开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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