{"title":"Low complexity OFDM receiver using Log-FFT for coded OFDM system","authors":"Yan Wang, H. Lam, C. Tsui, R. Cheng, W. Mow","doi":"10.1109/ISCAS.2002.1010256","DOIUrl":null,"url":null,"abstract":"In this paper, we describe a low complexity orthogonal frequency-division multiplexing (OFDM) receiver using Log-FFT for coded OFDM system. The complexity of the Log-FFT depends on the size of the look-up table, which is determined by the bit width of logarithmic number systems (LNS) representation. In coded OFDM system, simulation results show that there is no degradation in bit error rate performance when only two fractional bits are used for the LNS. As the bit width is so small, the look-up table can be easily implemented using a few combinational logic gates. Comparing the complexity and power consumption of the Log-FFT butterfly module with those of fixed point FFT butterfly module, about 60% reduction can be achieved.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2002.1010256","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, we describe a low complexity orthogonal frequency-division multiplexing (OFDM) receiver using Log-FFT for coded OFDM system. The complexity of the Log-FFT depends on the size of the look-up table, which is determined by the bit width of logarithmic number systems (LNS) representation. In coded OFDM system, simulation results show that there is no degradation in bit error rate performance when only two fractional bits are used for the LNS. As the bit width is so small, the look-up table can be easily implemented using a few combinational logic gates. Comparing the complexity and power consumption of the Log-FFT butterfly module with those of fixed point FFT butterfly module, about 60% reduction can be achieved.