{"title":"Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction","authors":"Aman Goel, K. Sakallah","doi":"10.1007/978-3-030-20652-9_11","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":436677,"journal":{"name":"NASA Formal Methods","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"NASA Formal Methods","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-030-20652-9_11","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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