Low-Ripple CMOS Switched-Capacitor Power Converter With Closed-Loop Interleaving Regulation

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.321004

Mohankumar N. Somasundaram, D. Ma

引用次数: 13

Abstract

This paper presents a new integrated switched-capacitor (SC) power converter with an interleaving regulation scheme. By dividing the original power stage into sub-units and operating each sub-unit in an interleaving way, the converter achieves attractive low ripple voltage and transient performance, without compromising other design parameters. The closed-loop operation ensures accurate voltage regulation at any desired levels. The design was fabricated with 0.35 mum CMOS N-well process. The die area including all pads and power transistors is 3.52 mm2. Measurement results show that, with a supply voltage of 1.5 V and a load current of 250 mA, the output of the converter is well regulated at 2.5 V with only 9-mV ripple. The maximum efficiency of 82.3 % is achieved, when the output power reaches 625 mW

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具有闭环交错调节的低纹波CMOS开关电容功率变换器

本文提出了一种采用交错调节方案的集成开关电容器(SC)功率变换器。通过将原始功率级划分为子单元，并以交错的方式运行每个子单元，转换器在不影响其他设计参数的情况下实现了具有吸引力的低纹波电压和瞬态性能。闭环操作确保准确的电压调节在任何所需的水平。设计采用0.35 μ m CMOS n阱工艺。包含所有焊盘和功率晶体管的芯片面积为3.52 mm2。测量结果表明，当电源电压为1.5 V，负载电流为250 mA时，变换器的输出可以很好地调节在2.5 V，纹波只有9 mv。当输出功率达到625 mW时，效率达到82.3%

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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IEEE Custom Integrated Circuits Conference 2006

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