Pub Date : 2006-12-01DOI: 10.1109/CICC.2006.320916
Jie Gu, J. Keane, S. Sapatnekar, C. Kim
This paper presents a statistical leakage estimation method for FinFET devices considering the unique width quantization property. Monte Carlo simulations show that the conventional approach underestimates the average leakage current of FinFET devices by as much as 43% while the proposed approach gives a precise estimation with an error less than 5%. Design example on dynamic logic circuits shows the effectiveness of the proposed method
{"title":"Width Quantization Aware FinFET Circuit Design","authors":"Jie Gu, J. Keane, S. Sapatnekar, C. Kim","doi":"10.1109/CICC.2006.320916","DOIUrl":"https://doi.org/10.1109/CICC.2006.320916","url":null,"abstract":"This paper presents a statistical leakage estimation method for FinFET devices considering the unique width quantization property. Monte Carlo simulations show that the conventional approach underestimates the average leakage current of FinFET devices by as much as 43% while the proposed approach gives a precise estimation with an error less than 5%. Design example on dynamic logic circuits shows the effectiveness of the proposed method","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/CICC.2006.320994
Kohei Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda, T. Sakurai
A chip-to-chip inductive wireless power transmission system is proposed and the feasibility is experimentally demonstrated for the first time. The circuit realized 2.5mW power transmission at the output DC voltage of 0.5V using 700 times 700mum on-chip planar inductors for the transmitter and the receiver. Methods to optimize the circuit design about the maximum transmission power and the simulated optimization results are discussed
{"title":"Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications","authors":"Kohei Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda, T. Sakurai","doi":"10.1109/CICC.2006.320994","DOIUrl":"https://doi.org/10.1109/CICC.2006.320994","url":null,"abstract":"A chip-to-chip inductive wireless power transmission system is proposed and the feasibility is experimentally demonstrated for the first time. The circuit realized 2.5mW power transmission at the output DC voltage of 0.5V using 700 times 700mum on-chip planar inductors for the transmitter and the receiver. Methods to optimize the circuit design about the maximum transmission power and the simulated optimization results are discussed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129375998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-12-01DOI: 10.1109/CICC.2006.320836
A. Tamtrakarn, H. Ishikuro, K. Ishida, T. Sakurai
This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD ). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit
{"title":"Compact outside-rail circuit structure by single-cascode two-transistor topology","authors":"A. Tamtrakarn, H. Ishikuro, K. Ishida, T. Sakurai","doi":"10.1109/CICC.2006.320836","DOIUrl":"https://doi.org/10.1109/CICC.2006.320836","url":null,"abstract":"This paper presents a new compact outside-rail circuit structure for future scaled CMOS technology. The proposed circuit is composed of only two transistors connected into a single cascode style for increasing supply voltage to one more nominal supply voltage (VDD ). The circuit is manufactured and measured. Reliability is also verified by the trajectory plot for gate-source voltage and gate-drain voltage of all devices. The results confirm that triple of nominal supply voltage can be used without any overstress in all CMOS devices. The proposed circuit saves 52% area and improves speed for 40% of the conventional approach in the case of 4VDD. An example of outside-rail opamp is also proposed by using the proposed circuit","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-10DOI: 10.1109/CICC.2006.320827
J.H.R. Schrader, E. Klumperink, J. Visschers, B. Nauta
High-speed data links over copper cables can be effectively equalized using pulse-width modulation (PWM) pre-emphasis. This provides an alternative to the usual 2-tap FIR filters. The use of PWM pre-emphasis allows a channel loss at the Nyquist frequency of ~30dB, compared to ~20dB for a 2-tap symbol-spaced FIR filter. The use of PWM fits well with future high-speed low-voltage CMOS processes. The filter has only one `knob', which is the duty-cycle. This makes convergence of an algorithm for automatic adaptation straightforward. Spectral analysis illustrates that, compared to a 2-tap FIR filter, the steeper PWM filter transfer function fits better to the copper channel. This applies to both half-symbol-spaced and symbol-spaced 2-tap FIR filters. Circuits for implementation are as straightforward as for FIR pre-emphasis. In this paper new measurements are presented for a previous transmitter chip, and a new high-swing transmitter chip is presented. Both coaxial and differential cables are used for the tests. A bit rate of 5 Gb/s (2-PAM) was achieved with all cable assemblies, over a cable length of up to 130 m. Measured BER at this speed is <10-12
{"title":"Wireline equalization using pulse-width modulation","authors":"J.H.R. Schrader, E. Klumperink, J. Visschers, B. Nauta","doi":"10.1109/CICC.2006.320827","DOIUrl":"https://doi.org/10.1109/CICC.2006.320827","url":null,"abstract":"High-speed data links over copper cables can be effectively equalized using pulse-width modulation (PWM) pre-emphasis. This provides an alternative to the usual 2-tap FIR filters. The use of PWM pre-emphasis allows a channel loss at the Nyquist frequency of ~30dB, compared to ~20dB for a 2-tap symbol-spaced FIR filter. The use of PWM fits well with future high-speed low-voltage CMOS processes. The filter has only one `knob', which is the duty-cycle. This makes convergence of an algorithm for automatic adaptation straightforward. Spectral analysis illustrates that, compared to a 2-tap FIR filter, the steeper PWM filter transfer function fits better to the copper channel. This applies to both half-symbol-spaced and symbol-spaced 2-tap FIR filters. Circuits for implementation are as straightforward as for FIR pre-emphasis. In this paper new measurements are presented for a previous transmitter chip, and a new high-swing transmitter chip is presented. Both coaxial and differential cables are used for the tests. A bit rate of 5 Gb/s (2-PAM) was achieved with all cable assemblies, over a cable length of up to 130 m. Measured BER at this speed is <10-12","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128896771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320991
V. Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, F. Woytowich, Bob Bassett
Performance verification is critical to high-performance ASICs manufacturing. Performance verification ensures that only those chips whose performance is higher than an advertised threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. At-speed structural test can provide performance verification capability at very low cost. In this paper, we present a scalable and flexible structural test method for performance verification of ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost
{"title":"Design For At-Speed Structural Test And Performance Verification Of High-Performance ASICs","authors":"V. Iyengar, Mark Johnson, Theo Anemikos, Gary Grise, Mark Taylor, Raymond Farmer, F. Woytowich, Bob Bassett","doi":"10.1109/CICC.2006.320991","DOIUrl":"https://doi.org/10.1109/CICC.2006.320991","url":null,"abstract":"Performance verification is critical to high-performance ASICs manufacturing. Performance verification ensures that only those chips whose performance is higher than an advertised threshold are shipped to demanding customers. This provides a means to weed out nominal performance ASICs, and also ship ASICs at difference grades. At-speed structural test can provide performance verification capability at very low cost. In this paper, we present a scalable and flexible structural test method for performance verification of ASICs. The proposed method requires no tight restrictions on the circuit design. Moreover, low-cost testers are used, thus sharply reducing test cost","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"54 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123080765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320892
Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seunghoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon
A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply
基于低功耗系统应用的开关偏置功耗降低技术，采用0.13 μ m CMOS实现的10b两级流水线ADC以25MS/s和10MS/s的双采样时钟速率工作。该原型ADC在高达25MS/s的所有采样速率下的最大SNDR和SFDR分别为56dB和65dB。ADC的有效芯片面积为0.8mm2，在1.2V电源下，在25MS/s和10MS/s分别消耗4.8mW和2.4mW
{"title":"A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications","authors":"Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seunghoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon","doi":"10.1109/CICC.2006.320892","DOIUrl":"https://doi.org/10.1109/CICC.2006.320892","url":null,"abstract":"A 10b two-stage pipeline ADC implemented in a 0.13mum CMOS operates at dual sampling clock rates of 25MS/s and 10MS/s based on a switched-bias power-reduction technique for low-power system applications. The prototype ADC shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling rates up to 25MS/s. The ADC occupies an active die area of 0.8mm2 and consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s, respectively, at a 1.2V supply","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125108938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320831
Guangmao Xing, S. Lewis, T. R. Viswanathan
A unity-gain buffer has been fabricated in 0.35-mum CMOS technology. The circuit uses feed forward and local feedback in a cascaded source follower circuit as well as two global feedback loops: one to reduce the output resistance, gain error, and offset and a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V and has a bandwidth of 92 MHz when driving a 13-pF capacitive load
采用0.35 μ m CMOS技术制备了单位增益缓冲器。该电路在级联源跟随电路中使用前馈和局部反馈以及两个全局反馈回路:一个回路用于减小输出电阻、增益误差和偏置，另一个回路用于进一步减小增益误差。该缓冲器在3.3 V时消耗3.7 mW，在驱动13-pF容性负载时带宽为92 MHz
{"title":"A Unity-Gain Buffer with Reduced Offset and Gain Error","authors":"Guangmao Xing, S. Lewis, T. R. Viswanathan","doi":"10.1109/CICC.2006.320831","DOIUrl":"https://doi.org/10.1109/CICC.2006.320831","url":null,"abstract":"A unity-gain buffer has been fabricated in 0.35-mum CMOS technology. The circuit uses feed forward and local feedback in a cascaded source follower circuit as well as two global feedback loops: one to reduce the output resistance, gain error, and offset and a second loop to further reduce gain error. The buffer consumes 3.7 mW at 3.3 V and has a bandwidth of 92 MHz when driving a 13-pF capacitive load","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126189160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320913
W. Oh, B. Bakkaloglu, B. Aravind, Siew Kuok Hoon
Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/radicHz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6musec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88mm2
低噪声、低差(LN-LDO)稳压器对于深亚微米模拟基带和射频片上系统设计的电源调节至关重要。提出了一种利用斩波稳定误差放大器的低1/f噪声LDO稳压器。为了实现负载瞬态的快速响应，设计了非对称输入对的电流型反馈放大器(CFA)作为第二级。斩波频率高达1MHz，在100kHz时可实现32nV/radicHz的输出噪声谱密度和38dB的PSR。与等效噪声密度的静态调节器相比，误差放大器的硅面积减少了75%。与同等功耗的电压模式缓冲器相比，电流模式反馈第二级缓冲器的稳定时间减少了60%，在50mA负载阶跃下达到0.6 μ c的稳定时间。LN-LDO采用0.25 μ m CMOS工艺设计和制造，具有五层金属，占地0.88mm2
{"title":"A Low 1/f Noise CMOS Low-Dropout Regulator with Current-Mode Feedback Buffer Amplifier","authors":"W. Oh, B. Bakkaloglu, B. Aravind, Siew Kuok Hoon","doi":"10.1109/CICC.2006.320913","DOIUrl":"https://doi.org/10.1109/CICC.2006.320913","url":null,"abstract":"Low-noise, low-dropout (LN-LDO) regulators are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low 1/f noise LDO regulator utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) with an asymmetrical input pair is designed as a second stage. With chopping frequencies up to 1MHz, an output noise spectral density of 32nV/radicHz and PSR of 38dB is achieved at 100kHz. Compared to an equivalent noise density static regulator, the error amplifier silicon area is reduced by 75%. With the current-mode feedback second stage buffer, settling time is reduced by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6musec settling time for a 50mA load step. The LN-LDO is designed and fabricated on a 0.25 mum CMOS process with five layers of metal, occupying 0.88mm2","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122902934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.321006
Janghoon Song, G. Yoon, Chulwoo Kim
A fast adaptive digital DC-DC converter for dynamic voltage scaling is presented. The control loop employs coarse and fine controls for each power transistor to enhance output response time and to reduce the conduction loss. The device was fabricated using a 0.18-mum CMOS process, occupying an area of 0.35mm2. The output voltage can vary from 0.76V to 1.75V, with a resolution of 28mV/step and a tracking time of 6.4 mus/V. Maximum efficiency of 94.8% is achieved with good load regulation
提出了一种用于动态电压标度的快速自适应数字DC-DC变换器。控制回路对每个功率晶体管采用粗控制和细控制，以提高输出响应时间并降低导通损耗。该器件采用0.18 μ m CMOS工艺制造，占地面积为0.35mm2。输出电压范围为0.76V ~ 1.75V，分辨率为28mV/步，跟踪时间为6.4 mus/V。负载调节良好，效率最高可达94.8%
{"title":"An Efficient Adaptive Digital DC-DC Converter with Dual Loop Controls for Fast Dynamic Voltage Scaling","authors":"Janghoon Song, G. Yoon, Chulwoo Kim","doi":"10.1109/CICC.2006.321006","DOIUrl":"https://doi.org/10.1109/CICC.2006.321006","url":null,"abstract":"A fast adaptive digital DC-DC converter for dynamic voltage scaling is presented. The control loop employs coarse and fine controls for each power transistor to enhance output response time and to reduce the conduction loss. The device was fabricated using a 0.18-mum CMOS process, occupying an area of 0.35mm2. The output voltage can vary from 0.76V to 1.75V, with a resolution of 28mV/step and a tracking time of 6.4 mus/V. Maximum efficiency of 94.8% is achieved with good load regulation","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122091859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-09-01DOI: 10.1109/CICC.2006.320960
J. Márkus, P. Deval, V. Quiquempoix, José B. Silva, G. Temes
In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinck filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sine filter is briefly discussed
{"title":"Incremental Delta-Sigma Structures for DC Measurement: an Overview","authors":"J. Márkus, P. Deval, V. Quiquempoix, José B. Silva, G. Temes","doi":"10.1109/CICC.2006.320960","DOIUrl":"https://doi.org/10.1109/CICC.2006.320960","url":null,"abstract":"In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed. Since line-frequency noise suppression is often important in measurement applications, modulators followed by sinck filters are also analyzed. Equations are derived for the estimation of the required number of cycles for a given resolution and architecture. Finally, the design and implementation of a third-order incremental converter with a fourth-order sine filter is briefly discussed","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129601870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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