ESD-capability Impacts of the RESURF NBL Length in High-voltage nLDMOSs

Abstract

In this paper, the Silvaco T-CAD software is used to simulate a high voltage n-LDMOS (lateral double-diffused metal oxide field-effect transistor) for a 0.18μm BCD process. The modulation of the N-type buried layer (NBL) has been adopted as an isolation layer to isolate ESD leakage into the substrate. In these devices, we divided the NBL into four partitions. Since the current is injected from the drain side, the NBL is used to isolation by reducing the modulation from the outer bulk side to 1/4 length of the inner drain side. Then there are five groups of this modulation including the full removal of the NBL layer. Eventually, it can be found that the trigger voltage (Vt1) increases obviously after all the NBL is removed, but we can find that the secondary breakdown current (It1) is reduced to only 0.65 A. When we reduced the NBL to only 1/4 of its length, the Vt1 and breakdown voltage (Vbk) also increased to 81.35(V), which is an increase of 32% compared to the reference group. At the same time It2 can be maintained at 1 A and the electric field value is reduced by 41% to 2.48e+3(V/cm). Therefore, the NBL reduction by only 1/4 (NBL_4) of these related components is the best modulation of this work.