Keynote speech 1: Leakage power in nanometric CMOS: Challenges and trends

Abstract

As technology is scaled down in the nanometric dimensions of the devices, the variability of the manufacturing process on the circuit parameters becomes critical. In addition, environmental changes in power supply voltages and temperature on chip gradients add new uncertainties on future electronic circuits and systems. The VLSI design paradigms are to be profoundly revised. The classical “design margin” approach to compensate for uncertainty becomes ineffective and costly. An emerging design approach consists in the provision of “on-chip adaptivity” to compensate dynamically to variability: Process parameters, Voltage, Temperature and Aging (PVTA).