Frequency compensation in two stage operational amplifier using common gate stage

Abstract

This paper represents a highly stable, more efficient and low power CMOS based operational amplifier. A compensation strategy using common gate stage is used which provides high gain-bandwidth product and overcomes the drawback of source follower and lead compensation approaches by eliminating the complex poles and right-half-plane (RHP) zero. The proposed circuit utilized the miller capacitance in conjunction with common gate current buffer to obtain the design equations. This circuit is simulated at 45nm technology using cadence analog virtuoso tool. The operational amplifier designed here produces an improved unity gain frequency of 6.8 MHZ with phase margin of approximately 68° and an open loop gain of 88 dB which ensures the stability of the system. The stability is required in high frequency switching regulators like sampled data system to generate their power supplies. These can also be used in a so many analog circuits such as active filters, analog-to-digital converters, low-dropout regulators (LDOs).