Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer

Abstract

Silicon interposers enable the heterogeneous integration in high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and a minimal trace width and spacing of 10 μm. We point out important advantages as well as differences of the chip-to-chip interconnection in comparison to an usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. We show by simulation that the electrical behavior of a 9 mm interconnection on the interposer is sufficient to drive a bus at 2 Gbit per second. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical printed circuit board transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical printed circuit board trace because of its increased resistance. Therefore we do not recommend to further decrease the minimal trace width for chip-to-chip interconnections.