Pub Date : 2015-11-01DOI: 10.1109/IMOC.2015.7369185
Richard Sjiariel
As a result of the increasing operating frequency and the number of transistors of IC, not only the signal integrity (SI), but the power integrity (PI) has also grown from non-existent to an important system. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE®. The accuracy of the simulation results are also compared with the measurement results.
随着集成电路工作频率和晶体管数量的不断增加，不仅信号完整性(SI)，而且功率完整性(PI)也从不存在发展成为一个重要的系统。电源完整性的目标是通过提供良好的电源为高速驱动器产生干净的信号。一个好的电源需要满足两个标准:1)满足直流功率要求，2)减少交流电流开关引起的功率波动。本文将讨论使用3D全波仿真工具CST STUDIO SUITE®进行电源完整性仿真。并将仿真结果与实测结果进行了比较。
{"title":"Power integrity simulation of power delivery network system","authors":"Richard Sjiariel","doi":"10.1109/IMOC.2015.7369185","DOIUrl":"https://doi.org/10.1109/IMOC.2015.7369185","url":null,"abstract":"As a result of the increasing operating frequency and the number of transistors of IC, not only the signal integrity (SI), but the power integrity (PI) has also grown from non-existent to an important system. The objective of power integrity is to produce a clean signal for the high-speed driver by supplying a good source. A good source needs to fulfill two criteria: 1) meet the DC power requirement and 2) reduce the power fluctuation caused by the AC current switch. This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE®. The accuracy of the simulation results are also compared with the measurement results.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237381
Michael Dittrich, A. Heinig
Silicon interposers enable the heterogeneous integration in high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and a minimal trace width and spacing of 10 μm. We point out important advantages as well as differences of the chip-to-chip interconnection in comparison to an usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. We show by simulation that the electrical behavior of a 9 mm interconnection on the interposer is sufficient to drive a bus at 2 Gbit per second. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical printed circuit board transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical printed circuit board trace because of its increased resistance. Therefore we do not recommend to further decrease the minimal trace width for chip-to-chip interconnections.
{"title":"Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer","authors":"Michael Dittrich, A. Heinig","doi":"10.1109/SAPIW.2015.7237381","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237381","url":null,"abstract":"Silicon interposers enable the heterogeneous integration in high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and a minimal trace width and spacing of 10 μm. We point out important advantages as well as differences of the chip-to-chip interconnection in comparison to an usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. We show by simulation that the electrical behavior of a 9 mm interconnection on the interposer is sufficient to drive a bus at 2 Gbit per second. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical printed circuit board transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical printed circuit board trace because of its increased resistance. Therefore we do not recommend to further decrease the minimal trace width for chip-to-chip interconnections.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237403
W. Dghais, Jonathan Rodriguez
This paper presents an analysis and extension of the input/output buffer information specification (IBIS) model's formulation and extraction based on the buffer issue resolution documents (BIRD) 98.3 and BIRD 95.6 to improve the signal and power integrity (SPI) prediction and evaluation under simultaneous switching noise (SSN) scenario. The performance and accuracy of the proposed model are evaluated in a SSN validation setup composed of three drivers.
{"title":"IBIS model formulation and extraction for SPI evaluation","authors":"W. Dghais, Jonathan Rodriguez","doi":"10.1109/SAPIW.2015.7237403","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237403","url":null,"abstract":"This paper presents an analysis and extension of the input/output buffer information specification (IBIS) model's formulation and extraction based on the buffer issue resolution documents (BIRD) 98.3 and BIRD 95.6 to improve the signal and power integrity (SPI) prediction and evaluation under simultaneous switching noise (SSN) scenario. The performance and accuracy of the proposed model are evaluated in a SSN validation setup composed of three drivers.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"46 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237396
A. Hardock, David Dahl, H. Bruns, C. Schuster
This paper presents an efficient computation of the static capacitance related to external fringing fields of vias (plated through holes) in printed circuit boards (PCBs). For this purpose, a numerical approach based on an integral equation for the surface charge density of axially symmetric geometries is used. The proposed method is validated with a commercial quasi-static tool. The capacitance model is applied to the modeling of typical PCB via stubs in the frequency range between 1 and 40 GHz. The results from the physics-based modeling are confirmed with a full-wave solver.
{"title":"Efficient calculation of external fringing capacitances for physics-based PCB modeling","authors":"A. Hardock, David Dahl, H. Bruns, C. Schuster","doi":"10.1109/SAPIW.2015.7237396","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237396","url":null,"abstract":"This paper presents an efficient computation of the static capacitance related to external fringing fields of vias (plated through holes) in printed circuit boards (PCBs). For this purpose, a numerical approach based on an integral equation for the surface charge density of axially symmetric geometries is used. The proposed method is validated with a commercial quasi-static tool. The capacitance model is applied to the modeling of typical PCB via stubs in the frequency range between 1 and 40 GHz. The results from the physics-based modeling are confirmed with a full-wave solver.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237405
J. Saade, Abdelaziz Goulahsen, A. Picco, Joel Huloux, F. Pétrot
Two main characteristics define the performance of a line coding: the maximum guaranteed run length (RL) which is the number of consecutive identical bits, and the running disparity (RD or DC-Balance) which is the difference between the number of “zeroes” and “ones” in a frame. Both should be bounded to a certain limit, RL to ensure reliable clock recovery and RD to limit baseline wander. In a previous paper, we presented a very low overhead line coding with guaranteed maximum run length. In this paper, we propose a low overhead technique to bound the running disparity that can do up to 10x better than existing encodings in terms of overhead and for the same RD bounds. We furthermore show how we can combine this technique with our former one to build a low overhead, run length limited, and DC-Balanced Line Coding.
{"title":"Low overhead, DC-Balanced and run length limited Line Coding","authors":"J. Saade, Abdelaziz Goulahsen, A. Picco, Joel Huloux, F. Pétrot","doi":"10.1109/SAPIW.2015.7237405","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237405","url":null,"abstract":"Two main characteristics define the performance of a line coding: the maximum guaranteed run length (RL) which is the number of consecutive identical bits, and the running disparity (RD or DC-Balance) which is the difference between the number of “zeroes” and “ones” in a frame. Both should be bounded to a certain limit, RL to ensure reliable clock recovery and RD to limit baseline wander. In a previous paper, we presented a very low overhead line coding with guaranteed maximum run length. In this paper, we propose a low overhead technique to bound the running disparity that can do up to 10x better than existing encodings in terms of overhead and for the same RD bounds. We furthermore show how we can combine this technique with our former one to build a low overhead, run length limited, and DC-Balanced Line Coding.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237401
InYoung Park, Ikchan Jang, Wonjoo Jung, Soyoung Kim
Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.
{"title":"Noise immunity modeling and analysis of delay-locked loop","authors":"InYoung Park, Ikchan Jang, Wonjoo Jung, Soyoung Kim","doi":"10.1109/SAPIW.2015.7237401","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237401","url":null,"abstract":"Delay-locked loops (DLLs) have emerged an attractive alternative to the traditional phase-locked loops (PLLs). It is essential to understand and analyze the electromagnetic susceptibility of DLLs to ensure the proper operation of the system. In order to ascertain how the performance of DLL is affected by the external noise, we design a DLL using self-biased techniques and establish the noise immunity experiment with bulk current injection (BCI) method. We also construct the equivalent circuit model for circuit simulation and demonstrate its validity by comparing with the measurement results. Consequently, the RF noise immunity characteristics of the DLL varies with its frequency and magnitude. Particularly, we detect that the DLL circuit that we designed is very sensitive to the external noise with frequency around 75 MHz.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115680228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237385
G. Signorini, C. Siviero, S. Grivet-Talocia, I. Stievano
This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.
{"title":"Power and Signal Integrity co-simulation via compressed macromodels of high-speed transceivers","authors":"G. Signorini, C. Siviero, S. Grivet-Talocia, I. Stievano","doi":"10.1109/SAPIW.2015.7237385","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237385","url":null,"abstract":"This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123901084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237383
Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim
In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.
{"title":"High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process","authors":"Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim","doi":"10.1109/SAPIW.2015.7237383","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237383","url":null,"abstract":"In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122657298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237389
K. Cai, S. Ji
A scalable power delivery analysis methodology is described for SoCs targeted at cost-driven platforms. The methodology is applied at different design stages to consolidate a hundred independent power supplies at bump level to half that at solder ball level and to five major power supplies at board level.
{"title":"Scalable power delivery design methodology for SoC on cost driven platforms","authors":"K. Cai, S. Ji","doi":"10.1109/SAPIW.2015.7237389","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237389","url":null,"abstract":"A scalable power delivery analysis methodology is described for SoCs targeted at cost-driven platforms. The methodology is applied at different design stages to consolidate a hundred independent power supplies at bump level to half that at solder ball level and to five major power supplies at board level.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130671250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237388
N. Chen
The high core count processor becomes the current trend to indicate the mobile devices' power. Mobile devices powered by octa-core CPUs offer faster performance, but suffer the larger dynamic voltage droops, especially for the PCB with the single-sided component placement (SSCP). Some chip-package-board co-simulations using the chip power model and full channel S-parameters were taken to evaluate the different decoupling capacitor configurations, feedback line designs, and the voltage compensation technique between the power management integrated circuit (PMIC) and the application processor (AP). Evaluation results indicated that the proposed single-ended feedback line sensed the most accurate voltage droop on the AP side than the traditional differential feedback lines did. A careful power distribution network design with the early voltage compensation technique reduced 37% of decoupling capacitor cost in the SSCP PCB and achieved the dynamic voltage droop on the AP side less than 10% of supply voltage from the PMIC.
{"title":"Designs of power distribution network for octa-core mobile application processor","authors":"N. Chen","doi":"10.1109/SAPIW.2015.7237388","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237388","url":null,"abstract":"The high core count processor becomes the current trend to indicate the mobile devices' power. Mobile devices powered by octa-core CPUs offer faster performance, but suffer the larger dynamic voltage droops, especially for the PCB with the single-sided component placement (SSCP). Some chip-package-board co-simulations using the chip power model and full channel S-parameters were taken to evaluate the different decoupling capacitor configurations, feedback line designs, and the voltage compensation technique between the power management integrated circuit (PMIC) and the application processor (AP). Evaluation results indicated that the proposed single-ended feedback line sensed the most accurate voltage droop on the AP side than the traditional differential feedback lines did. A careful power distribution network design with the early voltage compensation technique reduced 37% of decoupling capacitor cost in the SSCP PCB and achieved the dynamic voltage droop on the AP side less than 10% of supply voltage from the PMIC.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128139601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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