Circuit influences on COMFET™ (IGT) dynamic latching current

H. R. Ronan, C. Wheatley
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引用次数: 1

Abstract

Terminal measurements are made to verify that latching varies with gate drive resistance and occurs during turn off. dv/dt is varied from 1600 to 300 V/us with no impact on latch. A time-displaced turn-off current pulse demonstrates that latching occurs at very low drain voltages, suggesting a tailored gate drive. A brief discussion of device structure explains the observations.
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电路对COMFET™(IGT)动态锁存电流的影响
进行终端测量以验证锁存随栅极驱动电阻的变化而变化,并在关断期间发生。dv/dt从1600到300v /us变化,对锁存器没有影响。时间位移关断电流脉冲表明,锁存发生在极低的漏极电压,表明一个定制的栅极驱动。对器件结构的简要讨论解释了这些观察结果。
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