Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

Abstract

Process variation in current nanometer regime has recently emerged as a major concern in the design of very large scale integrated (VLSI) circuits including interconnect. Process variation leads to many uncertainties on circuit performances such as propagation delay. With the shrinking channel dimensions of MOSFET to nanometer scale, the performance of VLSI/ULSI chip becomes less predictable. The predictability of circuit performance may be reduced due to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper presents the variation of propagation delay through driver-interconnect-load (DIL) system due to various effects of interconnect parasitic. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies of 130nm, 70nm and 45nm. The comparison between these three technologies extensively shows that the effect of line resistive and capacitive parasitic variations on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is observed from 0.01% to 0.04% and −4.32% to 18.1% due to resistive and capacitive deviation of −6.1% to 25% respectively.