Extending VHDL to the systems level

Abstract

Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high-level design decisions. Although VHDL is an excellent digital system description language, it lacks the flexibility to address all systems-level issues. Digital system behavior and structure are effectively handled, but other facets are not. VSPEC represents one attempt to model other facets in the VHDL framework. It adds functional requirement and performance constraint modeling to the VHDL-based design process. This paper first describes VSPEC and its interaction with VHDL. It argues that VSPEC is an excellent first step towards a systems-level description language. However, other facets are needed to model complete systems. A language structure for representing these facets is proposed and a potential source for a semantic definition is identified.