Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623932
M. Mills
The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Cincinnati while under contract to Wright Laboratory. Conclusions are based on how well such object oriented extensions work with existing VHDL benefits to provide increased capabilities of the language and associated tools.
{"title":"A requirements analysis of proposed object oriented VHDL abstractions","authors":"M. Mills","doi":"10.1109/VIUF.1997.623932","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623932","url":null,"abstract":"The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Cincinnati while under contract to Wright Laboratory. Conclusions are based on how well such object oriented extensions work with existing VHDL benefits to provide increased capabilities of the language and associated tools.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125356167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623924
B. Kadrovach, P. Jarusiewic, B. C. Read, R. G. Bishop, L. Concha, K. Olson
The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics accelerator integrated circuit with approximately 700,000 transistors. The purpose of the methodology was to automate as much as possible the functional testing of all implementation levels. WAVES and its associated support tools provide a convenient method to quickly and accurately develop test benches for functional verification in VHDL at all levels. Additional tools were developed in-house to add capabilities for the testing and verification process. These added capabilities made WAVES useful for generating tests for gate and transistor models of the design components.
{"title":"Using WAVES for verification of synthesized sub-components in a deeply hierarchical design","authors":"B. Kadrovach, P. Jarusiewic, B. C. Read, R. G. Bishop, L. Concha, K. Olson","doi":"10.1109/VIUF.1997.623924","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623924","url":null,"abstract":"The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics accelerator integrated circuit with approximately 700,000 transistors. The purpose of the methodology was to automate as much as possible the functional testing of all implementation levels. WAVES and its associated support tools provide a convenient method to quickly and accurately develop test benches for functional verification in VHDL at all levels. Additional tools were developed in-house to add capabilities for the testing and verification process. These added capabilities made WAVES useful for generating tests for gate and transistor models of the design components.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623945
D. Soderberg
The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually.
{"title":"Extraction of token based VHDL models from old ASIC net lists","authors":"D. Soderberg","doi":"10.1109/VIUF.1997.623945","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623945","url":null,"abstract":"The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126603842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623953
M. D. McKinney
This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every action which was compliant with the IrLAP specification; and able to inject several different kinds of errors into the stimulus flow under user control. Embedding this level of stimulus strength, self-checking and user control was a challenge, but completing the component allowed the ASIC design team to field a fully verified interface which has needed no changes since its release to silicon.
{"title":"Building a test environment component in VHDL for an infrared link access protocol (IrLAP) compliant ASIC interface","authors":"M. D. McKinney","doi":"10.1109/VIUF.1997.623953","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623953","url":null,"abstract":"This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every action which was compliant with the IrLAP specification; and able to inject several different kinds of errors into the stimulus flow under user control. Embedding this level of stimulus strength, self-checking and user control was a challenge, but completing the component allowed the ASIC design team to field a fully verified interface which has needed no changes since its release to silicon.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127718206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623930
P. Ashenden, P. Wilsey, Donald E. K. Martin
The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. In addition to supporting object-orientation, these extended mechanisms improve the expressiveness of VHDL across the modeling spectrum, from high-level to gate-level. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. The paper outlines the SUAVE extensions and illustrates their use through some examples. The mechanisms and examples are readily understood as incremental extensions to current modeling practices, hence "painless extension".
{"title":"SUAVE: painless extension for an object-oriented VHDL","authors":"P. Ashenden, P. Wilsey, Donald E. K. Martin","doi":"10.1109/VIUF.1997.623930","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623930","url":null,"abstract":"The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. In addition to supporting object-orientation, these extended mechanisms improve the expressiveness of VHDL across the modeling spectrum, from high-level to gate-level. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. The paper outlines the SUAVE extensions and illustrates their use through some examples. The mechanisms and examples are readily understood as incremental extensions to current modeling practices, hence \"painless extension\".","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123283139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623925
S. Aftabjahani, Z. Navabi
A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be simulated using a standard VHDL simulator. A program for obtaining this model and creating a simulatable VHDL model has been developed. A comparison with other VHDL based fault simulations is given.
{"title":"Functional fault simulation of VHDL gate level models","authors":"S. Aftabjahani, Z. Navabi","doi":"10.1109/VIUF.1997.623925","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623925","url":null,"abstract":"A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be simulated using a standard VHDL simulator. A program for obtaining this model and creating a simulatable VHDL model has been developed. A comparison with other VHDL based fault simulations is given.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623950
R. Klenke, J. Aylor, B. W. Johnson, C. Choi, M. Meyassed, R. Rao, W. W. Dungan
This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have been made to ADEPT in the areas of mixed-level modeling-the cosimulation of performance and behavioral models, dependability modeling and analysis, modeling libraries, and post simulation data visualization tools, are presented.
{"title":"Improvements to ADEPT-a VHDL based integrated design environment for performance and dependability analysis","authors":"R. Klenke, J. Aylor, B. W. Johnson, C. Choi, M. Meyassed, R. Rao, W. W. Dungan","doi":"10.1109/VIUF.1997.623950","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623950","url":null,"abstract":"This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have been made to ADEPT in the areas of mixed-level modeling-the cosimulation of performance and behavioral models, dependability modeling and analysis, modeling libraries, and post simulation data visualization tools, are presented.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623955
J. Wedgwood, G. Buchanan
This paper describes our team's hardware model-year architecture (MYA) approach to develop cost-effective signal processors that can be applied to a wide range of military and commercial applications. We present an overview of the MYA approach and describe the framework. We introduce two key hardware architectural interfaces: the Standard Virtual Interface (SVI) and the Reconfigurable Network Interface (RNI). Next we describe several implementations of the SVI and RNI to illustrate how they would be used and some of the issues involved in implementing this approach. We discuss how the MYA relates to other efforts in the area of standard interfaces such as PCI (Peripheral Component Interconnect), PacketWay, the Virtual Microarchitecture Interface (VMI) and the Virtual Socket Interface Alliance (VSIA). Finally, we present our conclusions.
{"title":"A model-year architecture approach to hardware reuse in digital signal processor system design","authors":"J. Wedgwood, G. Buchanan","doi":"10.1109/VIUF.1997.623955","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623955","url":null,"abstract":"This paper describes our team's hardware model-year architecture (MYA) approach to develop cost-effective signal processors that can be applied to a wide range of military and commercial applications. We present an overview of the MYA approach and describe the framework. We introduce two key hardware architectural interfaces: the Standard Virtual Interface (SVI) and the Reconfigurable Network Interface (RNI). Next we describe several implementations of the SVI and RNI to illustrate how they would be used and some of the issues involved in implementing this approach. We discuss how the MYA relates to other efforts in the area of standard interfaces such as PCI (Peripheral Component Interconnect), PacketWay, the Virtual Microarchitecture Interface (VMI) and the Virtual Socket Interface Alliance (VSIA). Finally, we present our conclusions.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115373347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623937
Xavier'Warzee, P. Kajfasz, Thomson-CSF Optronique, P. Kajfasz
Presents our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded digital signal processing (DSP) systems. Instead of assuming one semantics (for instance, synchronous semantics) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements is challenging with such an approach. We propose an architectural view of systems which defines components and connectors to support respectively functional and non-functional requirements with several levels of abstraction specifying systems. Using the object-oriented framework Ptolemy, which supports simulating and prototyping of heterogeneous systems, a global view of the system is ensured, allowing us to validate its behavior and properties.
{"title":"Semantics based co-specifications to design DSP systems","authors":"Xavier'Warzee, P. Kajfasz, Thomson-CSF Optronique, P. Kajfasz","doi":"10.1109/VIUF.1997.623937","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623937","url":null,"abstract":"Presents our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded digital signal processing (DSP) systems. Instead of assuming one semantics (for instance, synchronous semantics) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements is challenging with such an approach. We propose an architectural view of systems which defines components and connectors to support respectively functional and non-functional requirements with several levels of abstraction specifying systems. Using the object-oriented framework Ptolemy, which supports simulating and prototyping of heterogeneous systems, a global view of the system is ensured, allowing us to validate its behavior and properties.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-10-19DOI: 10.1109/VIUF.1997.623944
T. Hadlich
The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal description languages at system level in comparison to VHDL is discussed. Concepts in regard to reconfigurable logic are discussed. An approach for a top-down methodology for this kind of logic is proposed.
{"title":"Use of VHDL within a system level design flow","authors":"T. Hadlich","doi":"10.1109/VIUF.1997.623944","DOIUrl":"https://doi.org/10.1109/VIUF.1997.623944","url":null,"abstract":"The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal description languages at system level in comparison to VHDL is discussed. Concepts in regard to reconfigurable logic are discussed. An approach for a top-down methodology for this kind of logic is proposed.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115141768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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