{"title":"An 8B/10B encoder with a modified coding table","authors":"Yong-Woo Kim, Jin-Ku Kang","doi":"10.1109/APCCAS.2008.4746322","DOIUrl":null,"url":null,"abstract":"This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.
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