An improved algorithm-driven methodology to optimize switched current memory cells by transistor sizing

International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04. Pub Date : 2004-09-05 DOI:10.1109/ICEEC.2004.1374569

M. Fakhfakh, M. Loulou, N. Masmoudi

引用次数: 22

Abstract

V C C I Abstract -In this paper, a design automation procedure is presented. It is an algorithm driven methodology which is capable of designing and optimizing SI circuits. we applied the proposed methodology to design optimal S21 class AB grounded gate memory cells. Owing to this procedure, this cell designed using the CMOS 0.35pm process under a single 3.3Vpower supply voltage, achieves 80 dB as dynamic range at 16 MHz sampling frequency. Besides it reaches less than 0.5 ns as settling time when priori@ is given to design high speed cells.

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通过晶体管尺寸优化开关电流存储单元的改进算法驱动方法

摘要:本文介绍了一种设计自动化程序。它是一种算法驱动的方法，能够设计和优化SI电路。我们应用所提出的方法来设计最佳的S21类AB接地门存储单元。因此，在3.3 v电源电压下，采用CMOS 0.35pm工艺设计的电池在16 MHz采样频率下，动态范围达到80 dB。并且在设计高速电池时，优先考虑的沉降时间小于0.5 ns。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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International Conference on Electrical, Electronic and Computer Engineering, 2004. ICEEC '04.

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