Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim
{"title":"A 4-bit 1.356 Gsps ADC for DS-CDMA UWB System","authors":"Ja-Hyun Koo, Yun-Jeong Kim, Bong-Hyuck Park, Sang-Seong Choi, Shin-Il Lim, Suki Kim","doi":"10.1109/ASSCC.2006.357920","DOIUrl":null,"url":null,"abstract":"In this paper, a 4-bit 1.356GS/S analog to digital (A/D) converter targeted for the direct spectrum code division multiple access ultra wide band (DS-CDMA UWB) is presented. The A/D converter uses a fully differential flash architecture. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input frequencies above 650 MHz with this current mode processing technique. The A/D converter achieves 3.7 effective number of bits (ENOBs) for a 30MHz sinusoidal input and 3.35 ENOBs for a 650 MHz input at a 1.356 GHz sampling rate. At 1.356 GS/s, the current consumption is 38 mA including digital logic with a power supply of 1.8V. The proposed A/D converter is fabricated using a 0.18-mum 6Metal lPoly CMOS process and the active area is 0.35 mm2.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357920","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
In this paper, a 4-bit 1.356GS/S analog to digital (A/D) converter targeted for the direct spectrum code division multiple access ultra wide band (DS-CDMA UWB) is presented. The A/D converter uses a fully differential flash architecture. To achieve low power consumption and high conversion rate, the proposed converter is designed with current mode amplifier (CMA) and each preamplifier includes a dual sense amplifier (DSA). The A/D converter can sample input frequencies above 650 MHz with this current mode processing technique. The A/D converter achieves 3.7 effective number of bits (ENOBs) for a 30MHz sinusoidal input and 3.35 ENOBs for a 650 MHz input at a 1.356 GHz sampling rate. At 1.356 GS/s, the current consumption is 38 mA including digital logic with a power supply of 1.8V. The proposed A/D converter is fabricated using a 0.18-mum 6Metal lPoly CMOS process and the active area is 0.35 mm2.