Race and Glitch Handling: A Test Perspective

Abstract

The paper summarizes practical logic structures creating race and/or glitch conditions which can cause incorrect test patterns. First, the design rule check (DRC) is proposed to identify such structures. Next, a novel methodology is proposed to handle such problematic structures during test generation to ensure the correctness of the test patterns with minimum test coverage loss. The proposed solution can seamlessly integrated into the automatic low coverage analysis to evaluate the test coverage impact and determine the root cause of major test coverage loss.