Pub Date : 2019-09-03DOI: 10.1109/ITC-Asia.2019.00032
Ahmed M. Y. Ibrahim, H. Kerkhoff
The IEEE 1687 standard defines a standardized mechanism for the off-chip access of embedded instruments. A subset of these instruments are also used for maintaining the reliability and functional safety of the chip during its lifetime. For example, temperature sensors, voltage monitors and Built-In-Self-Test engines. In this paper, we present a novel on-chip controller for IEEE 1687 networks which can execute instrument procedures documented in the IEEE 1687 PDL language. These procedures are incorporated within the reliability and functional safety embedded software that uses the measurements data of the instruments. The controller includes an efficient structural model of the IEEE 1687 network and can perform on-chip pattern retargeting on arbitrary networks. In addition, it can perform localization of instrument interrupts that are propagated via multi-mode IEEE 1687 networks.
{"title":"An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips","authors":"Ahmed M. Y. Ibrahim, H. Kerkhoff","doi":"10.1109/ITC-Asia.2019.00032","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00032","url":null,"abstract":"The IEEE 1687 standard defines a standardized mechanism for the off-chip access of embedded instruments. A subset of these instruments are also used for maintaining the reliability and functional safety of the chip during its lifetime. For example, temperature sensors, voltage monitors and Built-In-Self-Test engines. In this paper, we present a novel on-chip controller for IEEE 1687 networks which can execute instrument procedures documented in the IEEE 1687 PDL language. These procedures are incorporated within the reliability and functional safety embedded software that uses the measurements data of the instruments. The controller includes an efficient structural model of the IEEE 1687 network and can perform on-chip pattern retargeting on arbitrary networks. In addition, it can perform localization of instrument interrupts that are propagated via multi-mode IEEE 1687 networks.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130953478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/itc-asia.2019.00012
As SoCs continue to evolve to have more and more programmable elements and processors on them, the opportunity to tune the processors, interconnect and other blocks to match the intended application and gain advantages of performance and energy consumption is one that many designers are still not aware of. Experience on a wide variety of SoC designs has shown that significant increases in SoC performance and reduction in energy consumption are possible through the use of tuned ApplicationSpecific Instruction set Processors (ASIPs), along with the right choices of interconnect structures and associated hardware blocks. This embedded tutorial introduces the audience to the concept of ASIPs and uses practical examples to illustrate how ASIP architectures can be mapped to applications. It also covers a processor-centric design flow for complex SoC and in particular will describe models and methodologies for design, simulation and verification of these devices using the latest Electronic System Level (ESL) methods.
{"title":"Embedded Tutorial","authors":"","doi":"10.1109/itc-asia.2019.00012","DOIUrl":"https://doi.org/10.1109/itc-asia.2019.00012","url":null,"abstract":"As SoCs continue to evolve to have more and more programmable elements and processors on them, the opportunity to tune the processors, interconnect and other blocks to match the intended application and gain advantages of performance and energy consumption is one that many designers are still not aware of. Experience on a wide variety of SoC designs has shown that significant increases in SoC performance and reduction in energy consumption are possible through the use of tuned ApplicationSpecific Instruction set Processors (ASIPs), along with the right choices of interconnect structures and associated hardware blocks. This embedded tutorial introduces the audience to the concept of ASIPs and uses practical examples to illustrate how ASIP architectures can be mapped to applications. It also covers a processor-centric design flow for complex SoC and in particular will describe models and methodologies for design, simulation and verification of these devices using the latest Electronic System Level (ESL) methods.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126788056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00022
Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang
With the growing cost of powering and cooling, the Dynamic Voltage Frequency Scaling (DVFS) technique has been adopted in many mobiles and embedded devices nowadays. However, attackers are capable of maliciously manipulating the DVFS to threaten application programs including the security related ones. This paper first proposes a test method to test the vulnerabilities of CPU instructions under the DVFS attack. The test program feature, the testability of CPU instructions, and the Test Program Generation Algorithm (TPGA) are proposed. It is applied to an arm CPU in a mobile phone. Typical instructions are tested, and some are found vulnerable. Then, based on the test result, a method for code optimization by instruction substitution is proposed. The application program using vulnerable instructions are then attacked and optimized to prove the effectiveness of the proposed methods.
{"title":"Instruction Vulnerability Test and Code Optimization Against DVFS Attack","authors":"Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, Zhimin Zhang","doi":"10.1109/ITC-Asia.2019.00022","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00022","url":null,"abstract":"With the growing cost of powering and cooling, the Dynamic Voltage Frequency Scaling (DVFS) technique has been adopted in many mobiles and embedded devices nowadays. However, attackers are capable of maliciously manipulating the DVFS to threaten application programs including the security related ones. This paper first proposes a test method to test the vulnerabilities of CPU instructions under the DVFS attack. The test program feature, the testability of CPU instructions, and the Test Program Generation Algorithm (TPGA) are proposed. It is applied to an arm CPU in a mobile phone. Typical instructions are tested, and some are found vulnerable. Then, based on the test result, a method for code optimization by instruction substitution is proposed. The application program using vulnerable instructions are then attacked and optimized to prove the effectiveness of the proposed methods.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126443114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00040
Yousuke Miyake, S. Kajihara, Poki Chen
While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope.
{"title":"On-Chip Test Clock Validation Using A Time-to-Digital Converter in FPGAs","authors":"Yousuke Miyake, S. Kajihara, Poki Chen","doi":"10.1109/ITC-Asia.2019.00040","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00040","url":null,"abstract":"While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00018
Wei-Chen Huang, G. Hou, Jiun-Lang Huang, Terry Kuo
FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and roundtrip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.
{"title":"An FPGA-Based Data Receiver for Digital IC Testing","authors":"Wei-Chen Huang, G. Hou, Jiun-Lang Huang, Terry Kuo","doi":"10.1109/ITC-Asia.2019.00018","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00018","url":null,"abstract":"FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. In this paper, an FPGA-based test response receiver for digital IC testing is proposed. First, a three-stage round-trip-delay compensation scheme is introduced so that the strobe window can fully cover the test response window. Then, the corresponding characterization and calibration techniques are developed for the programmable delay line and roundtrip-delay. A prototype receiver is implemented on a Xilinx Spartan 6 FPGA; measurement results show that it is capable of 100 MHz sampling rate with 200 ps strobe position resolution.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133034372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00038
Tong-Yu Hsieh, Kuang-Chun Lin, Hsin-Hsien Lin
Implications have been shown to be beneficial for both concurrent error detection and diagnosis. To reduce the incurred hardware cost, one critical issue is selection of a minimum number of appropriate implications. Although the previous work developed several implication selection algorithms, the critical path delay may still be high. This is because the factors related to the critical path delay have not been well studied and considered during implication selection. In this paper, we investigate these factors and develop a new delay-aware implication selection algorithm. A buffer insertion algorithm is also developed such that the minimum number of buffers are inserted to further reduce the delay. This algorithm is integrated with the implication selection algorithm as a delay-aware implementation scheme. Experimental results on 18 ISCAS'85 and ITC'99 benchmark circuits show that 29.02% delay overhead reduction is achieved on average with only additional 0.34% implications selected.
{"title":"A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection","authors":"Tong-Yu Hsieh, Kuang-Chun Lin, Hsin-Hsien Lin","doi":"10.1109/ITC-Asia.2019.00038","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00038","url":null,"abstract":"Implications have been shown to be beneficial for both concurrent error detection and diagnosis. To reduce the incurred hardware cost, one critical issue is selection of a minimum number of appropriate implications. Although the previous work developed several implication selection algorithms, the critical path delay may still be high. This is because the factors related to the critical path delay have not been well studied and considered during implication selection. In this paper, we investigate these factors and develop a new delay-aware implication selection algorithm. A buffer insertion algorithm is also developed such that the minimum number of buffers are inserted to further reduce the delay. This algorithm is integrated with the implication selection algorithm as a delay-aware implementation scheme. Experimental results on 18 ISCAS'85 and ITC'99 benchmark circuits show that 29.02% delay overhead reduction is achieved on average with only additional 0.34% implications selected.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116196294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00035
Yang Yu, Zhiming Yang, Kangkang Xu
During the 3-D ICs manufacturing process, TSVs are susceptible to undergo different faults. Among these faults, the leakage fault is one of the most common cases. In this paper, a new test structure based on the improved ring oscillator circuit is proposed to detect the TSV leakage fault. An accurate TSV leakage fault model extracted from three-dimensional full-wave simulation is adopted in the test structure. HSPICE Monte Carlo simulation shows that the proposed test structure can detect the weak leakage faults with no less than 0.2025um2 pin-hole area, which is a larger coverage compared with the traditional test structure.
{"title":"A Post-Bond TSVs Test Solution for Leakage Fault","authors":"Yang Yu, Zhiming Yang, Kangkang Xu","doi":"10.1109/ITC-Asia.2019.00035","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00035","url":null,"abstract":"During the 3-D ICs manufacturing process, TSVs are susceptible to undergo different faults. Among these faults, the leakage fault is one of the most common cases. In this paper, a new test structure based on the improved ring oscillator circuit is proposed to detect the TSV leakage fault. An accurate TSV leakage fault model extracted from three-dimensional full-wave simulation is adopted in the test structure. HSPICE Monte Carlo simulation shows that the proposed test structure can detect the weak leakage faults with no less than 0.2025um2 pin-hole area, which is a larger coverage compared with the traditional test structure.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00027
A. Wahba, Chuanhe Jay Shan, Li-C. Wang, N. Sumikawa
This paper presents an automated flow to classify wafer plots obtained based on production test data. The wafer plots are based on pass/fail locations. The classification is achieved through wafer pattern recognition models built with two sets of techniques, Generative Adversarial Networks and Tensor analysis. The primary focus is on developing the automatic flow. Experiment results based on production test data from a microcontroller product line will be presented to demonstrate the usefulness of the proposed classification flow.
{"title":"Wafer Plot Classification Using Neural Networks and Tensor Methods","authors":"A. Wahba, Chuanhe Jay Shan, Li-C. Wang, N. Sumikawa","doi":"10.1109/ITC-Asia.2019.00027","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00027","url":null,"abstract":"This paper presents an automated flow to classify wafer plots obtained based on production test data. The wafer plots are based on pass/fail locations. The classification is achieved through wafer pattern recognition models built with two sets of techniques, Generative Adversarial Networks and Tensor analysis. The primary focus is on developing the automatic flow. Experiment results based on production test data from a microcontroller product line will be presented to demonstrate the usefulness of the proposed classification flow.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121206269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00031
Foisal Ahmed, Michihiro Shintani, M. Inoue
Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.
{"title":"Low Cost Recycled FPGA Detection Using Virtual Probe Technique","authors":"Foisal Ahmed, Michihiro Shintani, M. Inoue","doi":"10.1109/ITC-Asia.2019.00031","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00031","url":null,"abstract":"Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled fieldprogrammable gate arrays (FPGAs). On the other hand, it requires a large number of measurements of ROs for all FPGAs before shipping, and thus leads to measurement cost inflation. In this research, we propose a low-cost recycled FPGA detection method using a virtual probe (VP) technique based on compressed sensing. The VP technique enables us to accurately predict the spatial process variation on a die from a very small number of sample measurements. Using the estimated process variation as a supervisor, machine-learning algorithm classifies target FPGAs into recycled or fresh. Through experiments using circuit simulation, our method achieves more than 96% detection accuracy using one-class support vector machine where only 20% samples of the frequency are used at the best case. Silicon measurement results on Xilinx Artix-7 FPGAs also demonstrate the efficiencies of the proposed method.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-09-01DOI: 10.1109/ITC-Asia.2019.00034
R. P. Reddy, A. Acharyya, S. Khursheed
The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% – 9.05% and in 6T SRAM 2.51% – 4.76% and 3.77% – 5.64% decrease for storing 0 and 1 respectively.
{"title":"A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors","authors":"R. P. Reddy, A. Acharyya, S. Khursheed","doi":"10.1109/ITC-Asia.2019.00034","DOIUrl":"https://doi.org/10.1109/ITC-Asia.2019.00034","url":null,"abstract":"The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% – 9.05% and in 6T SRAM 2.51% – 4.76% and 3.77% – 5.64% decrease for storing 0 and 1 respectively.","PeriodicalId":348469,"journal":{"name":"2019 IEEE International Test Conference in Asia (ITC-Asia)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114663615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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