Mahin Esmaeilzadeh, Mohamed Ali, Ahmad Hassan, Y. Audet, M. Sawan
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引用次数: 2
Abstract
This paper presents a low-power large-bandwidth time-domain comparator. The proposed structure is constructed by two voltage-controlled oscillators (VCO) with enhanced linearity and a proposed glitch free and dead-zone free phase frequency detector (PFD). This novel VCO-based comparator is intended for monitoring and readout circuits in industrial sensor interfaces. The presented comparator has been implemented in a $0.35 \mu m$ standard CMOS process under $3.3 V$ supply voltage. This high accuracy comparator achieves $50 \mu V$ resolution and is able to operate at a frequency up to 400 MHz. The average power consumption of proposed design is $50.1 \mu W$, while occupying a silicon area of $0.004 mm^{2}$.