An efficient switch for fat tree Network-on-Chip interconnection architecture

Abstract

This paper describes a fat tree based Network-on-Chip (NOC) system. The fat tree includes processing nodes and communication switches. IP node has a message generator unit which randomly generates messages to different destinations with different packet lengths and buffering. Switches use wormhole routing with virtual channel mechanism. The switch consists of the following units: router, input/output link controllers and arbitration units. A simulator has been developed in C++ to analyze the proposed architecture. Moreover, a VHDL model for the employed algorithms has been simulated and prototyped (partially) in FPGA technology.