A Low SWaP-C Prototype Ka-Band Frequency Synthesizer for Atomic Clocks

Abstract

We present a low size, weight, power and cost (SWaP-C) prototype circuit of a Ka-band frequency synthesizer. It takes advantage of a phase-locked loop single integrated circuit (IC) and harmonic generation with high speed CMOS gates. We use a direct digital synthesizer (DDS) IC to tune the final output with micro-Hertz resolution. An ultra-low-power micro controller that could serve as the clock controller is used to control the PLL and the DDS. All components are commercial off the shelf (COTS) with acceptable industrial support. The total power consumption is about 1.6 Watt with −45 dBm useful output at 40.507347996 GHz. The short-term instability introduced by the prototype is 7.3E-14 at 1s. The prototyped subsystem uses COTS demonstration boards for the sake of agile prototyping. There is still significant margin for improvement of the size and weight.