{"title":"Heterogeneous Computing Platform for data processing","authors":"S. Prongnuch, T. Wiangtong","doi":"10.1109/ISPACS.2016.7824762","DOIUrl":null,"url":null,"abstract":"The Heterogeneous Computing Platform (HCP) contains the multiple types of processing elements which generally are CPUs, GPUs, and DSPs or FPGAs. In this platform, there must be mechanism to control both hardware processing elements and co-processing elements for computational intensive applications. The main challenge is to make all elements work together efficiently through Application Programming Interface (API). This paper proposes performance evaluation of APIs and Partial Reconfigurable (PR) hardware accelerator on HCP. In Parallella single board computer, PR hardware accelerator on Zynq-7000 SoC is created and compared with the uses of Epiphany 16-cores co-processor. Matrix-vector multiplications in different sized are implemented to measure accelerator's performance in different design aspects. The results show that when processing data is increasing, the PR hardware accelerator is the most promising one to run the platform efficiently.","PeriodicalId":131543,"journal":{"name":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"208 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS.2016.7824762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 13
Abstract
The Heterogeneous Computing Platform (HCP) contains the multiple types of processing elements which generally are CPUs, GPUs, and DSPs or FPGAs. In this platform, there must be mechanism to control both hardware processing elements and co-processing elements for computational intensive applications. The main challenge is to make all elements work together efficiently through Application Programming Interface (API). This paper proposes performance evaluation of APIs and Partial Reconfigurable (PR) hardware accelerator on HCP. In Parallella single board computer, PR hardware accelerator on Zynq-7000 SoC is created and compared with the uses of Epiphany 16-cores co-processor. Matrix-vector multiplications in different sized are implemented to measure accelerator's performance in different design aspects. The results show that when processing data is increasing, the PR hardware accelerator is the most promising one to run the platform efficiently.