Fast parallel application and multiprocessor design space exploration from sequential code

Abstract

When designing an application-specific multiprocessor, two key questions arise: (i) how to size the multiprocessor platform to meet application requirements with lowest area and power consumption; and (ii) how to parallelize the target application in order maximize the utilization of the platform. In this paper, we present a methodology for early joint parallel application and multiprocessor design space exploration from sequential application traces and parallelization scenarios. We describe its implementation in Parana, a fast trace-driven simulator, targeting OpenMP applications on the STMicroelectronics' STxP70 Application-Specific Multiprocessor. Results for a NAS Parallel Benchmark and two computer vision applications show an error margin of less than 10% compared to the reference cycle-approximate simulator, with lower modeling effort and one order of magnitude faster execution time.