Using mixed-mode test bus architecture to RF-based fault injection analysis and EMC fault debug

Abstract

The impressive development of RF communications observed last years with the intensive use of RF modules in several Mixed Signal Integrated Circuit as well as industrial and automotive qualification process, requiring engaged products compliant with aggressive EMC standards, introduces a challenge on the IC fault analysis. This work discuss a cost effective solution, small die size area using a Mixed Signal Test Bus Interface (Analog Test Bus more Digital Wrapper) aimed at small and medium complexity ICs. The proposed approach provides a powerful real time debug channel for RFI fault analysis and internal failure mechanism identification. This architecture was implemented in a silicon test vehicle, 0.25u BiCMOS technology, where measurements and results are presented and discussed.