A memory access system for merged memory with logic LSIs

Abstract

This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.