An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS

Abstract

We proposed an advanced minimization method for multiple valued multiple output functions in this paper. We extracted the shared sub functions with a proposed heuristic method to pair the functions. New minimization approach for multiple valued functions has also been proposed where we used Kleenean coefficients and we used LUT to reduce the complexity as well. Our minimization method reduces the number of implicants significantly. The realization of the minimized circuits has also been shown using current mode CMOS.