We present a case study in finding optimized processor architectures for a given protocol processing application. The process involves application analysis, hardware/software partitioning and optimization, and evaluation of design quality through simulations, estimations and synthesis. The case study was targeted at processing key IPv6 routing functions at 200 MHz using 0.18 /spl mu/m CMOS technology. A comparison to an implementation on a commercial processor revealed that the captured architectures provided similar or better performance. Especially checksum calculation was efficient in the captured architectures.
{"title":"Capturing processor architectures from protocol processing applications: a case study","authors":"S. Virtanen, J. Paakkulainen, T. Nurmi","doi":"10.1109/DSD.2005.23","DOIUrl":"https://doi.org/10.1109/DSD.2005.23","url":null,"abstract":"We present a case study in finding optimized processor architectures for a given protocol processing application. The process involves application analysis, hardware/software partitioning and optimization, and evaluation of design quality through simulations, estimations and synthesis. The case study was targeted at processing key IPv6 routing functions at 200 MHz using 0.18 /spl mu/m CMOS technology. A comparison to an implementation on a commercial processor revealed that the captured architectures provided similar or better performance. Especially checksum calculation was efficient in the captured architectures.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115128355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i. e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology.
{"title":"Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction","authors":"Dong Wu, B. Al-Hashimi, M. Schmitz, P. Eles","doi":"10.1109/DSD.2005.62","DOIUrl":"https://doi.org/10.1109/DSD.2005.62","url":null,"abstract":"Recent research has shown that the combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) yields high energy reductions in embedded systems. Nevertheless, the implementation of DVS and ABB requires a significant system cost, making it less attractive for many small systems. In this paper we demonstrate that it is possible to reduce this system cost and to achieve comparable energy saving to that obtained using combined DVS and ABB scheme through a co-synthesis methodology which is aware of the tasks' power-composition profile (the ratio of the dynamic power to the leakage power). In particular, the presented methodology performs a power management selection at the architectural level, i. e., it decides upon which processing elements to be equipped with which power management scheme (DVS, ABB, or combined DVS and ABB) - with the aim to achieve high energy savings at a reduced implementation cost. The proposed technique maps, schedules, and voltage scales applications specified as task graphs with timing constraints. Detailed experiments including a real-life benchmark are conducted to demonstrate the effectiveness of the proposed methodology.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115261275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a design and implementation of a reconfigurable parallel approximate string matching hardware on FPGAs. The design is based on a linear systolic dataflow algorithm, and control logic is added to reconfigure the resulting hardware. For the k-differences version of the approximate string matching problem, the proposed approach finds all approximate occurrences of a pattern in the reference string, with the time complexity O(n+m) where n and m are lengths of the reference string and the pattern, respectively. Unlike other hardware approaches found in the literature, the design is size optimized since it uses only m PEs that are independent on the reference string length. Also the design is flexible for handling arbitrary size pattern strings within the maximum bound. The design is implemented and tested on the target device Xilinx Spartan 2S XC2S200EPQ208.
{"title":"Reconfigurable parallel approximate string matching on FPGAs","authors":"J. H. Park","doi":"10.1109/DSD.2005.66","DOIUrl":"https://doi.org/10.1109/DSD.2005.66","url":null,"abstract":"This paper presents a design and implementation of a reconfigurable parallel approximate string matching hardware on FPGAs. The design is based on a linear systolic dataflow algorithm, and control logic is added to reconfigure the resulting hardware. For the k-differences version of the approximate string matching problem, the proposed approach finds all approximate occurrences of a pattern in the reference string, with the time complexity O(n+m) where n and m are lengths of the reference string and the pattern, respectively. Unlike other hardware approaches found in the literature, the design is size optimized since it uses only m PEs that are independent on the reference string length. Also the design is flexible for handling arbitrary size pattern strings within the maximum bound. The design is implemented and tested on the target device Xilinx Spartan 2S XC2S200EPQ208.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"303 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122822484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the design and performance measurements of a prototype wireless sensor network (WSN) for industrial linear position metering. Design includes two different prototype platforms and a user application. Prototypes combine energy efficient commercial off-the-shelf components including a 2.4 GHz radio, and the custom TUTWSN communication protocols resulting high robustness, autonomous operation and very low power consumption. The user application displays sensor data graphically and enables further data analysis. Measurements contain component power analysis and prototype performance measurements. The measurements indicate 200 /spl mu/W to 400 /spl mu/W average node power consumption, as 16-bit sample is measured with 1 Hz sample rate, and routed to a WSN gateway with 1 s latency per hop and 512 bps throughput between nodes. Predicted lifetime of implemented WSN is 2 months with a small rechargeable battery or over 2 years with two AA batteries.
{"title":"Wireless sensor network implementation for industrial linear position metering","authors":"M. Kohvakka, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/DSD.2005.78","DOIUrl":"https://doi.org/10.1109/DSD.2005.78","url":null,"abstract":"This paper presents the design and performance measurements of a prototype wireless sensor network (WSN) for industrial linear position metering. Design includes two different prototype platforms and a user application. Prototypes combine energy efficient commercial off-the-shelf components including a 2.4 GHz radio, and the custom TUTWSN communication protocols resulting high robustness, autonomous operation and very low power consumption. The user application displays sensor data graphically and enables further data analysis. Measurements contain component power analysis and prototype performance measurements. The measurements indicate 200 /spl mu/W to 400 /spl mu/W average node power consumption, as 16-bit sample is measured with 1 Hz sample rate, and routed to a WSN gateway with 1 s latency per hop and 512 bps throughput between nodes. Predicted lifetime of implemented WSN is 2 months with a small rechargeable battery or over 2 years with two AA batteries.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129721179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for our industry. Luckily, in the domain of multi-media, there exists a large body of functions where computational results need not always be correct. We show that for many VLSI implementations of signal processing algorithms, such as MPEG and JPEG encoders, a significant proportion of chips having low levels of defects provide erroneous but acceptable results. We introduce the concept of error-tolerance, and mention related issues needed to support this concept, including ways for specifying performance, design techniques that consider yield, test techniques for quantifying erroneous behavior, and finally the issue of marketing. The motivation for this work is to significantly increase the effective yield of a process, encourage the implementation of complex data processing chips, and drastically reduce chip costs.
{"title":"Multi-media applications and imprecise computation","authors":"M. Breuer","doi":"10.1109/DSD.2005.58","DOIUrl":"https://doi.org/10.1109/DSD.2005.58","url":null,"abstract":"As feature sizes continue to decrease and clock rates and device count on a VLSI chip increase, it becomes increasingly more difficult to maintain yields at their present levels. Process variation, noise and spot defects create very costly problems for our industry. Luckily, in the domain of multi-media, there exists a large body of functions where computational results need not always be correct. We show that for many VLSI implementations of signal processing algorithms, such as MPEG and JPEG encoders, a significant proportion of chips having low levels of defects provide erroneous but acceptable results. We introduce the concept of error-tolerance, and mention related issues needed to support this concept, including ways for specifying performance, design techniques that consider yield, test techniques for quantifying erroneous behavior, and finally the issue of marketing. The motivation for this work is to significantly increase the effective yield of a process, encourage the implementation of complex data processing chips, and drastically reduce chip costs.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Francisco Duarte, J. M. D. Silva, J. Alves, G. Pinho, J. S. Matos
This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.
{"title":"A processor for testing mixed-signal cores in system-on-chip","authors":"Francisco Duarte, J. M. D. Silva, J. Alves, G. Pinho, J. S. Matos","doi":"10.1109/DSD.2005.11","DOIUrl":"https://doi.org/10.1109/DSD.2005.11","url":null,"abstract":"This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114367918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the design of a remote fault simulator for delay faults that can be used by students to investigate the effect of different stimuli generators for different types of delay fault models.
{"title":"Remote path delay fault simulation","authors":"Øystein Gjermundnes, E. Aas","doi":"10.1109/DSD.2005.68","DOIUrl":"https://doi.org/10.1109/DSD.2005.68","url":null,"abstract":"This paper describes the design of a remote fault simulator for delay faults that can be used by students to investigate the effect of different stimuli generators for different types of delay fault models.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134582050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Traditionally, the embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems impossible for many companies, and in research facilities it hinders the testing of new research results with real embedded systems. We previously presented an easy and fast embedded system development concept based on embedded objects. The embedded object concept (EOC) utilizes common object oriented methods used in software by applying them to combined Lego-like software-hardware entities. This concept enables people without comprehensive knowledge in electronics design to create new embedded systems. In this paper we present a physical and logical architecture for this concept.
{"title":"Embedded object architecture","authors":"Tero Vallius, J. Röning","doi":"10.1109/DSD.2005.39","DOIUrl":"https://doi.org/10.1109/DSD.2005.39","url":null,"abstract":"Traditionally, the embedded system design process demands a considerable amount of expertise, time and money. This makes developing embedded systems impossible for many companies, and in research facilities it hinders the testing of new research results with real embedded systems. We previously presented an easy and fast embedded system development concept based on embedded objects. The embedded object concept (EOC) utilizes common object oriented methods used in software by applying them to combined Lego-like software-hardware entities. This concept enables people without comprehensive knowledge in electronics design to create new embedded systems. In this paper we present a physical and logical architecture for this concept.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129375685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Vitabile, V. Conti, Fulvio Gennaro, F. Sorbello
The efficiency and the accuracy of a digital feedforward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the hidden layer. The effectiveness of the proposed solutions has been evaluated developing different FPGA based neural prototypes for the high energy physics domain and the automatic road sign recognition domain. The use of the sinusoidal activation function decreases hardware resource employment of about 32% when compared with the standard sigmoid based neuron implementation. The virtual neuron implementation makes efficient the mapping of a neural network into hardware devices since it leads to a significant decreasing of concurrent memory access.
{"title":"Efficient MLP digital implementation on FPGA","authors":"S. Vitabile, V. Conti, Fulvio Gennaro, F. Sorbello","doi":"10.1109/DSD.2005.38","DOIUrl":"https://doi.org/10.1109/DSD.2005.38","url":null,"abstract":"The efficiency and the accuracy of a digital feedforward neural networks must be optimized to obtain both high classification rate and minimum area on chip. In this paper an efficient MLP digital implementation. The key features of the hardware implementation are the virtual neuron based architecture and the use of the sinusoidal activation function for the hidden layer. The effectiveness of the proposed solutions has been evaluated developing different FPGA based neural prototypes for the high energy physics domain and the automatic road sign recognition domain. The use of the sinusoidal activation function decreases hardware resource employment of about 32% when compared with the standard sigmoid based neuron implementation. The virtual neuron implementation makes efficient the mapping of a neural network into hardware devices since it leads to a significant decreasing of concurrent memory access.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.
{"title":"Efficient Implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures","authors":"M. Rawski, P. Tomaszewicz, H. Selvaraj, T. Luba","doi":"10.1109/DSD.2005.81","DOIUrl":"https://doi.org/10.1109/DSD.2005.81","url":null,"abstract":"This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach combinational LUT blocks replace general purpose multipliers, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper and application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124906374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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