{"title":"Efficient parallel finite field modular multiplier","authors":"Hua Li","doi":"10.1109/ISPA.2003.1296936","DOIUrl":null,"url":null,"abstract":"In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)/sup 2/ 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is T/sub AND/ + [log/sub 2/(m + 1)]T/sub XOR/. The proposed architectures are highly modular and well suited for high speed VLSI implementations.","PeriodicalId":218932,"journal":{"name":"3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPA.2003.1296936","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)/sup 2/ 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is T/sub AND/ + [log/sub 2/(m + 1)]T/sub XOR/. The proposed architectures are highly modular and well suited for high speed VLSI implementations.
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