Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies

Abstract

Inter-die and intra-die variation in process parameters increases parametric failures and leakage spread in nano-scale memories, leading to significant yield degradation. Design level optimization methods are not sufficient to address the leakage and parametric failures, particularly, under large variation. In this paper, we propose two post-silicon tuning techniques which can simultaneously reduce the leakage spread and improve parametric yield in memories. We show that, self- repairing and self-adaptive systems with post-silicon tuning are essential for designing low-power and robust memories in sub- 90 nm technologies.