45 GHz low power static frequency divider in 90 nm CMOS

Abstract

This work presents the design of a Q-band static frequency divider with quadrature signal output suitable for 60 GHz application. The RF performance improvement and power consumption reduction is achieved by using inductive peaking, resistor splitting techniques as well as proper transistor sizing. The static frequency divider is realized in a 90 nm CMOS technology with a chip area of 0.60×0.75 mm2. The self-oscillation frequency is 20.5 GHz with 12 GHz locking range. -16 dBm output power with less than -1 dBm input sensitivity were measured. The static frequency divider core and the output buffers consume 6.9 mW and 1.2 mW respectively from a 1.2 V power supply.