Pub Date : 2012-12-01DOI: 10.1109/RFIT.2012.6401673
Y. Uchida, Shihai He, Xin Yang, Qing Liu, T. Yoshimasu
In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-μπι CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output PldB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.
{"title":"5-GHz band linear CMOS power amplifier IC with a novel integrated linearizer for WLAN applications","authors":"Y. Uchida, Shihai He, Xin Yang, Qing Liu, T. Yoshimasu","doi":"10.1109/RFIT.2012.6401673","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401673","url":null,"abstract":"In this paper, novel linearization technique is proposed to realize a 5-GHz band linear CMOS power amplifier IC for WLAN application. The novel linearizer which consists of a diode-connected PMOS bias circuit and a PMOS varactor connected in parallel with an NMOS amplifier is effectively to suppress the gain compression and phase distortion of the power amplifier. A CMOS power amplifier IC is designed, fabricated and fully tested using TSMC 0.13-μπι CMOS technology. With these proposed techniques, the measurement results show a third-order IMD improvement of 9 dB over wide output power range and the maximum improvement of 18 dB. The power amplifier IC exhibits an output PldB of 19.5 dBm and a power gain of 9.5 dB at an operation voltage of 3.3 V.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128316066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/RFIT.2012.6401616
Tzuen-Hsi Huang, Sih-Han Li, P. Tsai, Chin-Chih Liu
This paper presents a dual-mode injection-locked frequency divider (ILFD) which can operate at 24 or 40 GHz. By a switchable band pass filter (BPF) design, the second harmonic of output frequency appeared at the common node of the differential injection pair can be either peaked or suppressed. At the same time, the fourth harmonic can be suppressed or peaked in contrary. The input injection signal can mix with the correspondingly peaked harmonic to achieve the division-by-3 or division-by-5 function. With an injection power level of +4 dBm, the locking ranges of 3.2 GHz (for division-by-3) and 880 MHz (for division-by-5) are achieved as the tuning voltage Vtune is fixed at 1.8 V. The total operation ranges for the division-by-3 and division-by-5 modes are from 22.5 to 27.0 GHz and from 38.23 to 41.55 GHz, respectively, as Vtune increases from 0 to 1.8 V. The divider core consumes 17.02 mW at 1 V supply voltage and the output buffers totally consume 3.0 mW at 1.8 V.
{"title":"Reconfigurable CMOS divide-by-3/-5 injection-locked frequency divider for dual-mode 24/40 GHz PLL application","authors":"Tzuen-Hsi Huang, Sih-Han Li, P. Tsai, Chin-Chih Liu","doi":"10.1109/RFIT.2012.6401616","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401616","url":null,"abstract":"This paper presents a dual-mode injection-locked frequency divider (ILFD) which can operate at 24 or 40 GHz. By a switchable band pass filter (BPF) design, the second harmonic of output frequency appeared at the common node of the differential injection pair can be either peaked or suppressed. At the same time, the fourth harmonic can be suppressed or peaked in contrary. The input injection signal can mix with the correspondingly peaked harmonic to achieve the division-by-3 or division-by-5 function. With an injection power level of +4 dBm, the locking ranges of 3.2 GHz (for division-by-3) and 880 MHz (for division-by-5) are achieved as the tuning voltage Vtune is fixed at 1.8 V. The total operation ranges for the division-by-3 and division-by-5 modes are from 22.5 to 27.0 GHz and from 38.23 to 41.55 GHz, respectively, as Vtune increases from 0 to 1.8 V. The divider core consumes 17.02 mW at 1 V supply voltage and the output buffers totally consume 3.0 mW at 1.8 V.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128358911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a Q-band balanced low noise amplifier (LNA) for radio astronomy applications is presented using 0.15-μm InGaAs metamorphic high electron mobility transistor (MHEMT) process. By using the balanced configuration, the input/output return losses and output 1-dB compression point of the LNA are improved. For the on-wafer measurement, the balanced LNA exhibits a broad bandwidth of from 27.3 to 50.7 GHz with a small-signal gain of 23.1 dB. The balanced LNA is further assembled in a packaged module for the cryogenic measurement. At a cryogenic temperature of 28 K, the average small-signal gain is higher than 19.5 dB from 30 to 50 GHz with the minimum equivalent noise temperature of 44.8 K. The proposed balanced LNA exhibits potential for radio astronomy applications due to its high small-signal gain, low noise, and low dc power consumption.
{"title":"A cryogenic 30–50 GHz balanced low noise amplifier using 0.15-μm MHEMT process for radio astronomy applications","authors":"Shou-Hsien Weng, Wei-chu Wang, Hong-Yeh Chang, Chau-Ching Chiong, Ming-Tang Chen","doi":"10.1109/RFIT.2012.6401652","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401652","url":null,"abstract":"In this paper, a Q-band balanced low noise amplifier (LNA) for radio astronomy applications is presented using 0.15-μm InGaAs metamorphic high electron mobility transistor (MHEMT) process. By using the balanced configuration, the input/output return losses and output 1-dB compression point of the LNA are improved. For the on-wafer measurement, the balanced LNA exhibits a broad bandwidth of from 27.3 to 50.7 GHz with a small-signal gain of 23.1 dB. The balanced LNA is further assembled in a packaged module for the cryogenic measurement. At a cryogenic temperature of 28 K, the average small-signal gain is higher than 19.5 dB from 30 to 50 GHz with the minimum equivalent noise temperature of 44.8 K. The proposed balanced LNA exhibits potential for radio astronomy applications due to its high small-signal gain, low noise, and low dc power consumption.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124465426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1007/978-1-4614-8896-5_2
Yuan Gao, Xin Liu, Yuanjin Zheng, Shengxi Diao, Wei-Da Toh, Yisheng Wang, Bin Zhao, M. Je, C. Heng
{"title":"A low power interference robust IR-UWB transceiver SoC for WBAN applications","authors":"Yuan Gao, Xin Liu, Yuanjin Zheng, Shengxi Diao, Wei-Da Toh, Yisheng Wang, Bin Zhao, M. Je, C. Heng","doi":"10.1007/978-1-4614-8896-5_2","DOIUrl":"https://doi.org/10.1007/978-1-4614-8896-5_2","url":null,"abstract":"","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116944061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401611
Sanming Hu, Y. Xiong, Lei Wang, Bolun Zhang
This paper presents a millimeter-wave (mmWave) mixer in 0.13μm SiGe HBT technology. The single-ended mixer is designed to down convert modulated mmWave signals with high speed up to 10Gbps. The on-wafer measured results show that, the fabricated 0.7mm × 0.5mm mixer exhibits a 10dB return-loss bandwidth covering the whole D-band (110-170GHz) at RF input port.
{"title":"A 135GHz single-ended mixer in 0.13μm SiGe HBT for high-speed demodulation","authors":"Sanming Hu, Y. Xiong, Lei Wang, Bolun Zhang","doi":"10.1109/RFIT.2012.6401611","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401611","url":null,"abstract":"This paper presents a millimeter-wave (mmWave) mixer in 0.13μm SiGe HBT technology. The single-ended mixer is designed to down convert modulated mmWave signals with high speed up to 10Gbps. The on-wafer measured results show that, the fabricated 0.7mm × 0.5mm mixer exhibits a 10dB return-loss bandwidth covering the whole D-band (110-170GHz) at RF input port.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122813574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401647
Tangsheng Chen, Jianjun Zhou, C. Ren, Zhonghui Li, Shichang Zhong, Bin Zhang
In this paper, a high power and high efficiency L/S-band GaN HEMT with tungsten nitride (WN) Schottky barrier is presented. By employing WN Schottky barrier, the reaction between the gate electrode and AlGaN layer is minimized and the Schottky barrier reveals good thermal stability. At 2.2 GHz, the developed GaN HEMT with 1.25 mm gate periphery delivers an output power density of 3.3W/mm with 75% maximum power-added efficiency (PAE). The accelerated life test shows that the mean time to failure (MTTF) of the developed devices is 1.8×107 hours at 150°C channel temperature with an activation energy of 1.5 e V. Output power more than 90 W and PAE about 70% are obtained with a 2×12 mm gate periphery packaged device between 1.14 GHz and 1.24 GHz.
{"title":"High power and high efficiency GaN HEMT with WN Schottky barrier","authors":"Tangsheng Chen, Jianjun Zhou, C. Ren, Zhonghui Li, Shichang Zhong, Bin Zhang","doi":"10.1109/RFIT.2012.6401647","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401647","url":null,"abstract":"In this paper, a high power and high efficiency L/S-band GaN HEMT with tungsten nitride (WN) Schottky barrier is presented. By employing WN Schottky barrier, the reaction between the gate electrode and AlGaN layer is minimized and the Schottky barrier reveals good thermal stability. At 2.2 GHz, the developed GaN HEMT with 1.25 mm gate periphery delivers an output power density of 3.3W/mm with 75% maximum power-added efficiency (PAE). The accelerated life test shows that the mean time to failure (MTTF) of the developed devices is 1.8×107 hours at 150°C channel temperature with an activation energy of 1.5 e V. Output power more than 90 W and PAE about 70% are obtained with a 2×12 mm gate periphery packaged device between 1.14 GHz and 1.24 GHz.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123815989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401663
L. Olivia, A. Kurniawan, Sugihartono, A. Munir
A square patch can operate whereby at the resonance frequency of resistively textured surface. The surface behaves like a perfect magnetic conductor; therefore the electric field would be in tangential to the surface. The developed patch that consists of square shape of metallic copper with length of 22mm and gap between patches of 2.0mm is placed on a single-sided 3.2mm thick grounded FR4 Epoxy dielectric substrate. Relative permittivity and tan δ of the dielectric substrate are 4.04 and 0.02, respectively, whilst the thickness of metallic copper top patch as well as the ground plane is 0.035mm. The losses of dielectric substrate and copper conductive are also taken into account. Surface-mounted-resistive elements are incorporated midway connecting between the adjacent patches to reduce the amount of backscatter from the surface. The reflection coefficient of absorber with resistive elements of 440Ω where upon the incident electromagnetic energy should be absorbed is up to 34dB.
{"title":"Characterization of radar absorber based on square patch textured surface","authors":"L. Olivia, A. Kurniawan, Sugihartono, A. Munir","doi":"10.1109/RFIT.2012.6401663","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401663","url":null,"abstract":"A square patch can operate whereby at the resonance frequency of resistively textured surface. The surface behaves like a perfect magnetic conductor; therefore the electric field would be in tangential to the surface. The developed patch that consists of square shape of metallic copper with length of 22mm and gap between patches of 2.0mm is placed on a single-sided 3.2mm thick grounded FR4 Epoxy dielectric substrate. Relative permittivity and tan δ of the dielectric substrate are 4.04 and 0.02, respectively, whilst the thickness of metallic copper top patch as well as the ground plane is 0.035mm. The losses of dielectric substrate and copper conductive are also taken into account. Surface-mounted-resistive elements are incorporated midway connecting between the adjacent patches to reduce the amount of backscatter from the surface. The reflection coefficient of absorber with resistive elements of 440Ω where upon the incident electromagnetic energy should be absorbed is up to 34dB.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114221296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401624
Xiangcheng Chen, C. Yuan, Y. Y. Lam
This paper presents a non-binary passive charge sharing SAR ADC and an optimization method for non-binary successive approximation algorithm. The passive charge sharing ADC is designed. The optimization method suggests that the non-binary SAR ADC with lower standard deviation DAC capacitance values will show better static performance. The SAR ADCs with different standard deviation value of DAC capacitor array are designed and simulated using a commercial 65nm CMOS technology. The simulation result shows that the static performance improvement trend is in accordance with the proposed optimization method. In addition, the optimized non-binary charge sharing SAR ADC shows better performance than conventional binary SAR ADC.
{"title":"Charge sharing non-binary SAR ADC","authors":"Xiangcheng Chen, C. Yuan, Y. Y. Lam","doi":"10.1109/RFIT.2012.6401624","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401624","url":null,"abstract":"This paper presents a non-binary passive charge sharing SAR ADC and an optimization method for non-binary successive approximation algorithm. The passive charge sharing ADC is designed. The optimization method suggests that the non-binary SAR ADC with lower standard deviation DAC capacitance values will show better static performance. The SAR ADCs with different standard deviation value of DAC capacitor array are designed and simulated using a commercial 65nm CMOS technology. The simulation result shows that the static performance improvement trend is in accordance with the proposed optimization method. In addition, the optimized non-binary charge sharing SAR ADC shows better performance than conventional binary SAR ADC.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401651
H. V. Le, H. T. Duong, C. Ta, A. Huynh, Robin J. Evans, E. Skafidas
This paper presents the design of a low noise amplifier (LNA) for automotive radar application operating at 76-77 GHz. The LNA consists of 5 cascade common source amplifiers. The output of each stage is positioned close to the gate of the next stage creating a LC resonance output load, therefore complex interstage matching networks are eliminated. Moreover, transmission lines (T Ls) are utilized to create matching and load inductors. As a result, chip size is significantly reduced. The proposed LNA is implemented in a 65 nm CMOS technology and measurement results show 11 dB voltage gain, and 7.8 dB noise figure (NF) while dissipating 21.5 mA from 1.2 V supply.
{"title":"A 77 GHz CMOS low noise amplifier for automotive radar receiver","authors":"H. V. Le, H. T. Duong, C. Ta, A. Huynh, Robin J. Evans, E. Skafidas","doi":"10.1109/RFIT.2012.6401651","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401651","url":null,"abstract":"This paper presents the design of a low noise amplifier (LNA) for automotive radar application operating at 76-77 GHz. The LNA consists of 5 cascade common source amplifiers. The output of each stage is positioned close to the gate of the next stage creating a LC resonance output load, therefore complex interstage matching networks are eliminated. Moreover, transmission lines (T Ls) are utilized to create matching and load inductors. As a result, chip size is significantly reduced. The proposed LNA is implemented in a 65 nm CMOS technology and measurement results show 11 dB voltage gain, and 7.8 dB noise figure (NF) while dissipating 21.5 mA from 1.2 V supply.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131409889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-01DOI: 10.1109/RFIT.2012.6401656
W. Y. Lim, Jinglin Shi, M. A. Arasu, M. Je
In this paper, we have developed equivalent scalable inductor models for symmetrically octagonal spiral inductors. Adjustable parameters include number of turns (Nturn), inner diameter (D), width (W) and spacing (S) of inductors with models being scaled over a wide specification range. A complementary frequency independent scalable 4-PI model are presented for accurate modeling When compared with simulation and measurement results, the models exhibit an error percentage for inductance at 1 GHz / 5 GHz at within ±10 %, error percentage for Q-peak (Peak Quality factor) is within ±20 % and error percentage for self resonant frequency (SRF) is within ±7 %.
{"title":"Geometric scalable 2-port center-tap inductor modeling","authors":"W. Y. Lim, Jinglin Shi, M. A. Arasu, M. Je","doi":"10.1109/RFIT.2012.6401656","DOIUrl":"https://doi.org/10.1109/RFIT.2012.6401656","url":null,"abstract":"In this paper, we have developed equivalent scalable inductor models for symmetrically octagonal spiral inductors. Adjustable parameters include number of turns (Nturn), inner diameter (D), width (W) and spacing (S) of inductors with models being scaled over a wide specification range. A complementary frequency independent scalable 4-PI model are presented for accurate modeling When compared with simulation and measurement results, the models exhibit an error percentage for inductance at 1 GHz / 5 GHz at within ±10 %, error percentage for Q-peak (Peak Quality factor) is within ±20 % and error percentage for self resonant frequency (SRF) is within ±7 %.","PeriodicalId":187550,"journal":{"name":"2012 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114328726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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