A CMOS analog four-quadrant multiplier for CNN synapses

Abstract

This work presents a new architecture of analog four-quadrant multiplier in CMOS technology based on the behavior of MOSFET in the linear region from weak to strong inversion. The proposed multiplier has voltage and current inputs and a current output, thus being adequate for the implementation of compact synapses in analog Cellular Neural Network (CNN). Simulation results exhibit low power consumption and low distortion.