Efficient Hardware/Software partitioning for Heterogeneous Embedded Systems

Abstract

This paper presents a novel model-based hardware/software co-design methodology applied to heterogeneous embedded platforms. A time-predictable hardware and software co-design architecture design is proposed. The proposed technique is based on floating point operations analysis and is intended to be applied for real-time applications at an early stage of the design, to assist the designer taking the right considerations in choosing the most effective Hardware/Software partitioning. The design analysis is carried out on the MATLAB model of the application, and is demonstrated for a specific voice activation algorithm. A Data Flow Graph (DFG) representation is used to represent the various operational blocks of the chosen algorithm. An efficient decomposition of the design operational blocks into a fixed software processor and alternative extensible hardware components is carefully carried out to find the correct balance between flexibility and performance with respect to power consumption and size, and the demands related to time predictability. Experimental results demonstrate that the proposed algorithm performs a significant area saving factor of 39% and power consumption reduction of 19%, while applied to voice activation module within the same system constraints.