{"title":"Towards a chip level reliability simulator for copper/low-k backend processes","authors":"M. Bashir, L. Milor","doi":"10.1109/DATE.2010.5457195","DOIUrl":null,"url":null,"abstract":"A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DATE.2010.5457195","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
A framework is proposed to analyze circuit layout geometries to predict chip lifetime due to low-k time-dependent dielectric breakdown (TDDB). The methodology uses as inputs data from test structures, which have been designed and fabricated to detect the impact of area and metal linewidth on low-k TDDB.
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