Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457165
B. Alorda, G. Torrens, S. Bota, J. Segura
The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.
{"title":"Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs","authors":"B. Alorda, G. Torrens, S. Bota, J. Segura","doi":"10.1109/DATE.2010.5457165","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457165","url":null,"abstract":"The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116653219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457155
Zhang Tao, Tao Lv, Xiaowei Li
In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.
{"title":"An abstraction-guided simulation approach using Markov models for microprocessor verification","authors":"Zhang Tao, Tao Lv, Xiaowei Li","doi":"10.1109/DATE.2010.5457155","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457155","url":null,"abstract":"In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116961864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457199
Dirk Diekhoff
Dirk Diekhoff, Elektrobit Automotive “The development of complex control units requires mature and reliable basic software as well as integration support particularly in early phases of the project. In this presentation Elektrobit Automotive will focus on new AUTOSAR basic software features such as multi core and functional safety. We will show how integration and validation will be enhanced by diagnostic logging and tracing functionalities.”
{"title":"AUTOSAR basic software for complex control units","authors":"Dirk Diekhoff","doi":"10.1109/DATE.2010.5457199","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457199","url":null,"abstract":"Dirk Diekhoff, Elektrobit Automotive “The development of complex control units requires mature and reliable basic software as well as integration support particularly in early phases of the project. In this presentation Elektrobit Automotive will focus on new AUTOSAR basic software features such as multi core and functional safety. We will show how integration and validation will be enhanced by diagnostic logging and tracing functionalities.”","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"347 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120942303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457186
A. Krupp, W. Müller
Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.
{"title":"A systematic approach to the test of combined HW/SW systems","authors":"A. Krupp, W. Müller","doi":"10.1109/DATE.2010.5457186","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457186","url":null,"abstract":"Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120959841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457145
Michael Karner, E. Armengaud, C. Steger, R. Weiss
Automotive network technologies such as FlexRay present a cost-optimized structure in order to tailor the system to the required functionalities and to the environment. The space exploration for optimization of single components (cable, transceiver, communication controller, middleware, application) as well as the integration of these components (e.g. selection of the topology) are complex activities that can be efficiently supported by means of simulation. The main challenge while simulating communication architectures is to efficiently integrate the heterogeneous models in order to obtain accurate results for a relevant operation time of the system. In this work, a run-time model switching method is introduced for the holistic simulation of FlexRay networks. Based on a complete modeling of the main network components, the simulation performance increase is analyzed and the new test and diagnosis possibilities resulting from this holistic approach are discussed.
{"title":"Holistic simulation of FlexRay networks by using run-time model switching","authors":"Michael Karner, E. Armengaud, C. Steger, R. Weiss","doi":"10.1109/DATE.2010.5457145","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457145","url":null,"abstract":"Automotive network technologies such as FlexRay present a cost-optimized structure in order to tailor the system to the required functionalities and to the environment. The space exploration for optimization of single components (cable, transceiver, communication controller, middleware, application) as well as the integration of these components (e.g. selection of the topology) are complex activities that can be efficiently supported by means of simulation. The main challenge while simulating communication architectures is to efficiently integrate the heterogeneous models in order to obtain accurate results for a relevant operation time of the system. In this work, a run-time model switching method is introduced for the holistic simulation of FlexRay networks. Based on a complete modeling of the main network components, the simulation performance increase is analyzed and the new test and diagnosis possibilities resulting from this holistic approach are discussed.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy consumption has always been considered as the key issue of the state-of-the-art SoCs. Implementing an on-chip Cache is one of the most promising solutions. However, traditional Cache may suffer from performance and energy penalties due to the Cache conflict. In order to deal with this problem, this paper firstly introduces a Time-Slotted Cache Conflict Graph to model the behavior of Data Cache conflict. Then, we implement an Integer Nonlinear Programming to select the most profitable data pages and employ Virtual Memory System to remap those data pages, which can cause severe Cache conflict within a time slot, to the on-chip Scratchpad Memory (SPM). In order to minimize the swapping overhead of dynamic SPM allocation, we introduce a novel SPM controller with a tightly coupled DMA to issue the swapping operations without CPU's intervention. The proposed method can optimize all of the data segments, including global data, heap and stack data in general, and reduce 24.83% energy consumption on average without any performance degradation.
{"title":"Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph","authors":"Huanan Wang, Yang Zhang, Chen Mei, Ming Ling","doi":"10.5555/1870926.1871067","DOIUrl":"https://doi.org/10.5555/1870926.1871067","url":null,"abstract":"Energy consumption has always been considered as the key issue of the state-of-the-art SoCs. Implementing an on-chip Cache is one of the most promising solutions. However, traditional Cache may suffer from performance and energy penalties due to the Cache conflict. In order to deal with this problem, this paper firstly introduces a Time-Slotted Cache Conflict Graph to model the behavior of Data Cache conflict. Then, we implement an Integer Nonlinear Programming to select the most profitable data pages and employ Virtual Memory System to remap those data pages, which can cause severe Cache conflict within a time slot, to the on-chip Scratchpad Memory (SPM). In order to minimize the swapping overhead of dynamic SPM allocation, we introduce a novel SPM controller with a tightly coupled DMA to issue the swapping operations without CPU's intervention. The proposed method can optimize all of the data segments, including global data, heap and stack data in general, and reduce 24.83% energy consumption on average without any performance degradation.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116019570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457032
Özgün Paker, Sebastian Eckert, A. Bury
We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2×2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK,QPSK,16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2×6 softbits worst-case every 10 clock cycles).
{"title":"A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture","authors":"Özgün Paker, Sebastian Eckert, A. Bury","doi":"10.1109/DATE.2010.5457032","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457032","url":null,"abstract":"We present an algorithm and architecture of a soft-output sphere decoder with an optimized hardware implementation for 2×2 MIMO-OFDM reception. We introduce a novel table look-up approach for symbol enumeration that simplifies the implementation of soft-output decoders. The HW implementation is targeted towards WLAN (IEEE 802.11n) with stringent latency and throughput requirements. The current implementation supports all modulation schemes (BPSK,QPSK,16-QAM, 64-QAM) and shows near-optimal real-time performance. To achieve this, the sphere decoder computes in the worst-case Euclidean distances of 4.1 Giga QAM symbols per second. This challenging requirement is met by a scalable, multi-standard HW architecture which can be tuned to other applications such as LTE, WiMax with no re-design effort. The current instance for WLAN occupies an area of only 0.17 mm2 in 45 nm CMOS technology while providing a guaranteed throughput of 374 Msoftbits/s at 312 MHz clock rate (i.e. outputting 2×6 softbits worst-case every 10 clock cycles).","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"488 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116030134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457095
S. López, R. Sarmiento, Philip G. Potter, W. Luk, P. Cheung
Hardware sharing can be used to reduce the area and the power dissipation of a design. This is of particular interest in the field of image and video compression, where an encoder must deal with different design tradeoffs depending on the characteristics of the signal to be encoded and the constraints imposed by the users. This paper introduces a novel methodology for exploring the design space based on the amount of hardware sharing between different functional blocks, giving as a result a set of feasible solutions which are broad in terms of hardware cost and throughput capabilities. The proposed approach, inspired by the notion of a partition in set theory, has been applied to optimize and to evaluate the sharing alternatives of a group of image and video compression key computational kernels when mapped onto a Xilinx Virtex-5 FPGA.
{"title":"Exploration of hardware sharing for image encoders","authors":"S. López, R. Sarmiento, Philip G. Potter, W. Luk, P. Cheung","doi":"10.1109/DATE.2010.5457095","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457095","url":null,"abstract":"Hardware sharing can be used to reduce the area and the power dissipation of a design. This is of particular interest in the field of image and video compression, where an encoder must deal with different design tradeoffs depending on the characteristics of the signal to be encoded and the constraints imposed by the users. This paper introduces a novel methodology for exploring the design space based on the amount of hardware sharing between different functional blocks, giving as a result a set of feasible solutions which are broad in terms of hardware cost and throughput capabilities. The proposed approach, inspired by the notion of a partition in set theory, has been applied to optimize and to evaluate the sharing alternatives of a group of image and video compression key computational kernels when mapped onto a Xilinx Virtex-5 FPGA.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122914350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5456924
Alessio Bonfietti, L. Benini, M. Lombardi, M. Milano
Our work focuses on allocating and scheduling a synchronous data-flow (SDF) graph onto a multi-core platform subject to a minimum throughput requirement. This problem has traditionally be tackled by incomplete approaches based on problem decomposition and local search, which could not guarantee optimality. Exact algorithms used to be considered reasonable only for small problem instances. We propose a complete algorithm based on Constraint Programming which solves the allocation and scheduling problem as a whole. We introduce a number of search acceleration techniques that significantly reduce run-time by aggressively pruning the search space without compromising optimality. The solver has been tested on a number of non-trivial instances and demonstrated promising run-times on SDFGs of practical size and one order of magnitude speed-up w.r.t. the fastest known complete approach.
{"title":"An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms","authors":"Alessio Bonfietti, L. Benini, M. Lombardi, M. Milano","doi":"10.1109/DATE.2010.5456924","DOIUrl":"https://doi.org/10.1109/DATE.2010.5456924","url":null,"abstract":"Our work focuses on allocating and scheduling a synchronous data-flow (SDF) graph onto a multi-core platform subject to a minimum throughput requirement. This problem has traditionally be tackled by incomplete approaches based on problem decomposition and local search, which could not guarantee optimality. Exact algorithms used to be considered reasonable only for small problem instances. We propose a complete algorithm based on Constraint Programming which solves the allocation and scheduling problem as a whole. We introduce a number of search acceleration techniques that significantly reduce run-time by aggressively pruning the search space without compromising optimality. The solver has been tested on a number of non-trivial instances and demonstrated promising run-times on SDFGs of practical size and one order of magnitude speed-up w.r.t. the fastest known complete approach.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129847291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-08DOI: 10.1109/DATE.2010.5457041
C. Ferent, Varun Subramanian, Michael Gilberti, A. Doboli
Cyber Physical Systems are distributed systems-of-systems that integrate sensing, processing, networking and actuation. Aggregating physical data over space and in time emerges as an intrinsic part of data acquisition, and is critical for dependable decision making under performance and resource constraints. This paper presents a Linear Programming-based method for optimizing the aggregation of data sampled from geographically-distributed areas while satisfy timing, precision, and resource constraints. The paper presents experimental results for data aggregation, including a case study on gas detection using a network of sensors.
{"title":"Linear programming approach for performance-driven data aggregation in networks of embedded sensors","authors":"C. Ferent, Varun Subramanian, Michael Gilberti, A. Doboli","doi":"10.1109/DATE.2010.5457041","DOIUrl":"https://doi.org/10.1109/DATE.2010.5457041","url":null,"abstract":"Cyber Physical Systems are distributed systems-of-systems that integrate sensing, processing, networking and actuation. Aggregating physical data over space and in time emerges as an intrinsic part of data acquisition, and is critical for dependable decision making under performance and resource constraints. This paper presents a Linear Programming-based method for optimizing the aggregation of data sampled from geographically-distributed areas while satisfy timing, precision, and resource constraints. The paper presents experimental results for data aggregation, including a case study on gas detection using a network of sensors.","PeriodicalId":432902,"journal":{"name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123482807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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