The use of short cycle test chips to accelerate yield learning during the start up of a 150 mm fabrication facility

Abstract

A set of electrically tested, short cycle test chips and a methodology were developed to derive yield improvement during the transfer of 1.0 mu m and 0.8 mu m CMOS technologies from high-volume 100-mm facilities to a 150-mm fabrication facility. This resulted in a rapid drop of defect density and the correction of many systematic yield problems before full process lots were affected. The design of the test devices and the methodology is important to the success of the effort utilizing simple, statistically valid, large-scale arrays in the test chips, and a Pareto-driven, brutal focus analysis and improvement methodology. An analysis of shortcomings of using electrically tested structures only was done and possible improvements using optical defect detection equipment were identified.<>