Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148149
Chitra K. Subramanian, G. Neudeck
A full-wafer silicon-on-insulator (SOI) process using epitaxial lateral overgrowth is demonstrated. Merged selective epitaxial growth of silicon was used to create local area SOI islands. Chemical-mechanical polishing was used to form well-controlled submicrometer-thick single-crystal SOI film using local area nitride as etch stops. Epitaxial lateral growth which was initiated from a vertical seed is demonstrated. The technique produces a generic full-wafer SOI structure. To obtain multiple layers of silicon over oxide, this SOI process can be repeated several times without damage to the previously formed layers and therefore makes three-dimensional integration possible.<>
{"title":"A full-wafer SOI process for 3 dimensional integration","authors":"Chitra K. Subramanian, G. Neudeck","doi":"10.1109/UGIM.1991.148149","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148149","url":null,"abstract":"A full-wafer silicon-on-insulator (SOI) process using epitaxial lateral overgrowth is demonstrated. Merged selective epitaxial growth of silicon was used to create local area SOI islands. Chemical-mechanical polishing was used to form well-controlled submicrometer-thick single-crystal SOI film using local area nitride as etch stops. Epitaxial lateral growth which was initiated from a vertical seed is demonstrated. The technique produces a generic full-wafer SOI structure. To obtain multiple layers of silicon over oxide, this SOI process can be repeated several times without damage to the previously formed layers and therefore makes three-dimensional integration possible.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"118 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148118
J. Hudson, R. Gutmann
The authors describe a series of curricula at the Master's level that have been developed at Rensselaer over the last three years. The curricula are aimed at producing graduates who have both a working knowledge of microelectronics manufacturing, and the general background necessary to conceive and implement process or product improvements. The description includes both the content of the curricula developed in terms of course work and laboratory experiences, and the means of delivery and delivery options developed to maximize access to the program by students from a wide variety of backgrounds and circumstances. The authors assess the results of this program, both in terms of the program output and in terms of the relation of this program to the graduate program at Rensselaer in general.<>
{"title":"The microelectronics manufacturing engineering program at Rensselaer Polytechnic Institute","authors":"J. Hudson, R. Gutmann","doi":"10.1109/UGIM.1991.148118","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148118","url":null,"abstract":"The authors describe a series of curricula at the Master's level that have been developed at Rensselaer over the last three years. The curricula are aimed at producing graduates who have both a working knowledge of microelectronics manufacturing, and the general background necessary to conceive and implement process or product improvements. The description includes both the content of the curricula developed in terms of course work and laboratory experiences, and the means of delivery and delivery options developed to maximize access to the program by students from a wide variety of backgrounds and circumstances. The authors assess the results of this program, both in terms of the program output and in terms of the relation of this program to the graduate program at Rensselaer in general.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148139
J. McDaniel, D. Moursund, C. Silsby, J. Winnett
A set of electrically tested, short cycle test chips and a methodology were developed to derive yield improvement during the transfer of 1.0 mu m and 0.8 mu m CMOS technologies from high-volume 100-mm facilities to a 150-mm fabrication facility. This resulted in a rapid drop of defect density and the correction of many systematic yield problems before full process lots were affected. The design of the test devices and the methodology is important to the success of the effort utilizing simple, statistically valid, large-scale arrays in the test chips, and a Pareto-driven, brutal focus analysis and improvement methodology. An analysis of shortcomings of using electrically tested structures only was done and possible improvements using optical defect detection equipment were identified.<>
开发了一套电测试、短周期测试芯片和一种方法，用于将1.0 μ m和0.8 μ m CMOS技术从大批量的100毫米设备转移到150毫米制造设备，从而提高产量。这导致缺陷密度迅速下降，并在整个工艺批次受到影响之前纠正了许多系统良率问题。测试设备和方法的设计对于在测试芯片中使用简单、统计有效、大规模阵列以及帕累托驱动的、残酷的焦点分析和改进方法的努力的成功是重要的。分析了仅使用电测试结构的缺点，并确定了使用光学缺陷检测设备可能进行的改进
{"title":"The use of short cycle test chips to accelerate yield learning during the start up of a 150 mm fabrication facility","authors":"J. McDaniel, D. Moursund, C. Silsby, J. Winnett","doi":"10.1109/UGIM.1991.148139","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148139","url":null,"abstract":"A set of electrically tested, short cycle test chips and a methodology were developed to derive yield improvement during the transfer of 1.0 mu m and 0.8 mu m CMOS technologies from high-volume 100-mm facilities to a 150-mm fabrication facility. This resulted in a rapid drop of defect density and the correction of many systematic yield problems before full process lots were affected. The design of the test devices and the methodology is important to the success of the effort utilizing simple, statistically valid, large-scale arrays in the test chips, and a Pareto-driven, brutal focus analysis and improvement methodology. An analysis of shortcomings of using electrically tested structures only was done and possible improvements using optical defect detection equipment were identified.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148128
Y. Chiou, C. Sow, G. Li, J. Gambino, P. J. Tsang
The I-V characteristics of thin SiO/sub 2/ films with thicknesses ranging from 35 to 250 AA were studied using conventional Al-gate MOS capacitors prepared on <100> p-type substrate as the test vehicle. Several measurement techniques including constant voltage, constant current, and voltage pulse were used. Consistent results have been obtained. time-dependent currents were observed in the low field region, i.e. less than 8 MV/cm for oxides thicker than 50 AA due to displacement currents and charge trapping. The slope of the Fowler-Nordheim plot is sensitive to the way the oxide field is estimated. For thicker oxides (greater than 100 AA), the slope may have a value between 240 approximately 300 MV/cm depending on the estimated oxide field. For thinner oxides, the slope is smaller due to the enhancement in the direct tunneling effect.<>
{"title":"Current conduction in thermally grown thin SiO/sub 2/ films","authors":"Y. Chiou, C. Sow, G. Li, J. Gambino, P. J. Tsang","doi":"10.1109/UGIM.1991.148128","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148128","url":null,"abstract":"The I-V characteristics of thin SiO/sub 2/ films with thicknesses ranging from 35 to 250 AA were studied using conventional Al-gate MOS capacitors prepared on <100> p-type substrate as the test vehicle. Several measurement techniques including constant voltage, constant current, and voltage pulse were used. Consistent results have been obtained. time-dependent currents were observed in the low field region, i.e. less than 8 MV/cm for oxides thicker than 50 AA due to displacement currents and charge trapping. The slope of the Fowler-Nordheim plot is sensitive to the way the oxide field is estimated. For thicker oxides (greater than 100 AA), the slope may have a value between 240 approximately 300 MV/cm depending on the estimated oxide field. For thinner oxides, the slope is smaller due to the enhancement in the direct tunneling effect.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129450701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148115
Y. Shamash, R. Massengale
The authors describe the research and teaching programs of the National Science Foundation Center for the Design of analog/digital integrated circuits. The Center was established through a partnership between universities, state governments, the federal government, and industry. The center has been in existence for almost two years with a current industrial membership of fourteen. There are seventeen faculty members, from three universities, participating in the research programs and over thirty graduate and undergraduate students. The programs has already had a significant impact on graduate and undergraduate courses at the universities. A review is given of the various features needed to ensure success in bringing industry, universities, and government together to work on a problem of joint interest.<>
{"title":"University/government/industry program in analog/digital integrated circuits","authors":"Y. Shamash, R. Massengale","doi":"10.1109/UGIM.1991.148115","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148115","url":null,"abstract":"The authors describe the research and teaching programs of the National Science Foundation Center for the Design of analog/digital integrated circuits. The Center was established through a partnership between universities, state governments, the federal government, and industry. The center has been in existence for almost two years with a current industrial membership of fourteen. There are seventeen faculty members, from three universities, participating in the research programs and over thirty graduate and undergraduate students. The programs has already had a significant impact on graduate and undergraduate courses at the universities. A review is given of the various features needed to ensure success in bringing industry, universities, and government together to work on a problem of joint interest.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114733001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148155
A. Kabir, J. Pak, G. Neudeck, J. Logsdon, D. DeRoo, S. E. Staller
A novel epitaxial growth and micromachining technology were used for form a thin single-crystal silicon diaphragm for micromechanical sensors. Merged epitaxial lateral overgrowth (MELO) of silicon and SiO/sub 2/ etch-stop technology were successfully used to fabricate a diaphragm with a precise thickness. Its implementation to the formation of a large thin diaphragm is demonstrated. The silicon epitaxial growth rate is the only controlling parameter to define the diaphragm thickness. An average growth uniformity of the MELO film across the three-inch wafers was determined to be less than 5%. However, the average percentage variation of the growth at the same position on the wafer, from wafer to wafer in a single run, was measured to be within 2%. Diaphragms of 9+or-0.05 mu m thick and more than 200 mu m wide and 1000 mu m long were successfully fabricated using this technique.<>
{"title":"A novel method of forming a thin single crystal silicon diaphragm with precise thickness for potential use in fabricating micromechanical sensors using merged epitaxial lateral overgrowth","authors":"A. Kabir, J. Pak, G. Neudeck, J. Logsdon, D. DeRoo, S. E. Staller","doi":"10.1109/UGIM.1991.148155","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148155","url":null,"abstract":"A novel epitaxial growth and micromachining technology were used for form a thin single-crystal silicon diaphragm for micromechanical sensors. Merged epitaxial lateral overgrowth (MELO) of silicon and SiO/sub 2/ etch-stop technology were successfully used to fabricate a diaphragm with a precise thickness. Its implementation to the formation of a large thin diaphragm is demonstrated. The silicon epitaxial growth rate is the only controlling parameter to define the diaphragm thickness. An average growth uniformity of the MELO film across the three-inch wafers was determined to be less than 5%. However, the average percentage variation of the growth at the same position on the wafer, from wafer to wafer in a single run, was measured to be within 2%. Diaphragms of 9+or-0.05 mu m thick and more than 200 mu m wide and 1000 mu m long were successfully fabricated using this technique.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114482860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148121
A.R. La Pietra, L. Fuller
A five-mask-level, isolated bipolar process was developed. Phosphorous was selectively implanted and annealed into p-type wafers to form the electrically isolated n-wells, and a double diffusion process was used to create active devices inside the n-wells. Several bipolar transistors and simple circuits were successfully fabricated and tested over three developmental processing runs.<>
{"title":"An ion-implanted N-well bipolar process for university analog integrated circuit fabrication","authors":"A.R. La Pietra, L. Fuller","doi":"10.1109/UGIM.1991.148121","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148121","url":null,"abstract":"A five-mask-level, isolated bipolar process was developed. Phosphorous was selectively implanted and annealed into p-type wafers to form the electrically isolated n-wells, and a double diffusion process was used to create active devices inside the n-wells. Several bipolar transistors and simple circuits were successfully fabricated and tested over three developmental processing runs.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148125
L. Fuller, S. Blondell, J. Tierney
Rochester Institute of Technology (RIT) has been operating a large integrated circuit laboratory for over four years. Approximately $750000 per year is donated equipment and supplies from industry, leaving a cost of $315000 per year for operating this facility. Approximately $100000 per year is available from RIT funds the remaining $215000 is raised by an industrial associates program. Twenty one companies each donate $10000 per year for these operating expenses. These companies include some of the affiliate companies who are beyond the first three-year commitment as well as other companies interested in supporting the microelectronic engineering program at RIT.<>
{"title":"A cost analysis of operating a large integrated circuit laboratory at Rochester Institute of Technology","authors":"L. Fuller, S. Blondell, J. Tierney","doi":"10.1109/UGIM.1991.148125","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148125","url":null,"abstract":"Rochester Institute of Technology (RIT) has been operating a large integrated circuit laboratory for over four years. Approximately $750000 per year is donated equipment and supplies from industry, leaving a cost of $315000 per year for operating this facility. Approximately $100000 per year is available from RIT funds the remaining $215000 is raised by an industrial associates program. Twenty one companies each donate $10000 per year for these operating expenses. These companies include some of the affiliate companies who are beyond the first three-year commitment as well as other companies interested in supporting the microelectronic engineering program at RIT.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148120
D. Langford, K. Rambo, T. Fox, T. Back, C. Pañeda
An integrated circuit fabrication facility has been developed at the University of Florida which is suitable for undergraduate laboratories, research in process technology, and studies in DFM (design for manufacturability). The NMOS process described represents the first step toward the long-range goal of developing a CMOS technology. The design goals for the University of Florida NMOS (UF NMOS) process were to check the performance limits of the fabrication facilities and to develop a process flow which could be integrated into a one semester undergraduate laboratory. Processing capabilities include ion implantation and low-pressure chemical vapor deposition (LPCVD) of polysilicon and silicon dioxide. The availability of these processes allows design of an all-implanted technology including threshold-adjustment implants and polysilicon gates with a self-aligned MOS structure. The process description is given. Process design tools and layout tools are described. Testing procedures are outlined, and the laboratory implementation is discussed. Measured data flow from NMOS devices are included.<>
{"title":"Development of a poly-gate NMOS process for research and teaching","authors":"D. Langford, K. Rambo, T. Fox, T. Back, C. Pañeda","doi":"10.1109/UGIM.1991.148120","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148120","url":null,"abstract":"An integrated circuit fabrication facility has been developed at the University of Florida which is suitable for undergraduate laboratories, research in process technology, and studies in DFM (design for manufacturability). The NMOS process described represents the first step toward the long-range goal of developing a CMOS technology. The design goals for the University of Florida NMOS (UF NMOS) process were to check the performance limits of the fabrication facilities and to develop a process flow which could be integrated into a one semester undergraduate laboratory. Processing capabilities include ion implantation and low-pressure chemical vapor deposition (LPCVD) of polysilicon and silicon dioxide. The availability of these processes allows design of an all-implanted technology including threshold-adjustment implants and polysilicon gates with a self-aligned MOS structure. The process description is given. Process design tools and layout tools are described. Testing procedures are outlined, and the laboratory implementation is discussed. Measured data flow from NMOS devices are included.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125461571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1991-06-12DOI: 10.1109/UGIM.1991.148150
R. D. Butler, R. E. Beaty
A microelectronic process allowing successful fabrication of polysilicon gate and replacement metal gate devices on the same die is described. The characteristics of aluminium replaced gate devices are compared to those of coexistent polysilicon gate devices showing agreement with theoretical predictions. Following standard processing, plasma back-etching steps are used to form the replacement gates. Virtually any material which can be deposited and patterned on silicon dioxide can be used as the replacement gate material.<>
{"title":"MOS fabrication process integrating self-aligned polysilicon gate and post-processed metal gate devices on a single die","authors":"R. D. Butler, R. E. Beaty","doi":"10.1109/UGIM.1991.148150","DOIUrl":"https://doi.org/10.1109/UGIM.1991.148150","url":null,"abstract":"A microelectronic process allowing successful fabrication of polysilicon gate and replacement metal gate devices on the same die is described. The characteristics of aluminium replaced gate devices are compared to those of coexistent polysilicon gate devices showing agreement with theoretical predictions. Following standard processing, plasma back-etching steps are used to form the replacement gates. Virtually any material which can be deposited and patterned on silicon dioxide can be used as the replacement gate material.<<ETX>>","PeriodicalId":163406,"journal":{"name":"Proceedings Ninth Biennial University/Government/Industry Microelectronics Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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