High level testbench generation for VHDL models

Abstract

A new technique for automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language (K. Sapiecha and S. Deniziak, 1996) and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.